參數(shù)資料
型號： 9DB1933AKLF
廠商： INTEGRATED DEVICE TECHNOLOGY INC
元件分類： 時鐘及定時
英文描述： 9DB SERIES, PLL BASED CLOCK DRIVER, 19 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQCC72
封裝： ROHS COMPLIANT, PLASTIC, QFN-72
文件頁數(shù)： 14/17頁
文件大?。?/td> 174K
代理商： 9DB1933AKLF
IDT
Nineteen Output Differential Buffer for PCIe Gen3
9DB1933
Nineteen Output Differential Buffer for PCIe Gen3
6
1676A—07/12/10
Electrical Characteristics - Clock Input Parameters
TA = TCOM or TIND; Supply Voltage VDD = 3.3 V +/-5%
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS NOTES
Input High Voltage - DIF_IN
VIHDIF
Differential inputs
(single-ended measurement)
600
800
1150
mV
1
Input Low Voltage - DIF_IN
VILDIF
Differential inputs
(single-ended measurement)
VSS - 300
0
300
mV
1
Input Common Mode
Voltage - DIF_IN
VCOM
Common Mode Input Voltage
300
1000
mV
1
Input Amplitude - DIF_IN
VSWING
Peak to Peak value
300
1450
mV
1
Input Slew Rate - DIF_IN
dv/dt
Measured differentially
0.4
8
V/ns
1,2
Input Leakage Current
IIN
VIN = VDD , VIN = GND
-5
5
uA
1
Input Duty Cycle
dtin
Measurement from differential wavefrom
45
55
%
1
Input Jitter - Cycle to Cycle
JDIFIn
Differential Measurement
0
125
ps
1
1 Guaranteed by design and characterization, not 100% tested in production.
2Slew rate measured through +/-75mV window centered around differential zero
Electrical Characteristics - DIF 0.7V Current Mode Differential Outputs
TA = TCOM; Supply Voltage VDD = 3.3 V +/-5%
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS NOTES
Slew rate
Trf
Scope averaging on
124
V/ns
1, 2, 3
Slew rate matching
ΔTrf
Slew rate matching, Scope averaging on
20
%
1, 2, 4
Voltage High
VHigh
660
789
850
1
Voltage Low
VLow
-150
45
150
1
Max Voltage
Vmax
834
1150
1
Min VoltageVmin
-300
17
1
Vswing
Scope averaging off
300
744
mV
1, 2
Crossing Voltage (abs)
Vcross_abs
Scope averaging off
250
380
550
mV
1, 5
Crossing Voltage (var)
Δ-Vcross
Scope averaging off
24
140
mV
1, 6
2 Measured from differential waveform
6 The total variation of all Vcross measurements in any particular system. Note that this is a subset of V_cross_min/max (V_cross absolute)
allowed. The intent is to limit Vcross induced modulation by setting V_cross_delta to be smaller than V_cross absolute.
mV
Statistical measurement on single-ended signal
using oscilloscope math function. (Scope averaging
on)
Measurement on single ended signal using absolute
value. (Scope averaging off)
mV
1Guaranteed by design and characterization, not 100% tested in production. IREF = VDD/(3xR
R). For RR = 475 (1%), IREF = 2.32mA. IOH =
6 x IREF and VOH = 0.7V @ ZO=50 (100
Ω differential impedance).
3 Slew rate is measured through the Vswing voltage range centered around differential 0V. This results in a +/-150mV window around
differential 0V.
4 Matching applies to rising edge rate of Clock / falling edge rate of Clock#. It is measured in a +/-75mV window centered on the average
cross point where Clock rising meets Clock# falling. The median cross point is used to calculate the voltage thresholds the oscilloscope uses
for the edge rate calculations.
5 Vcross is defined as voltage where Clock = Clock# measured on a component test board and only applies to the differential rising edge (i.e.
Clock rising and Clock# falling).
Electrical Characteristics - Current Consumption
TA = TCOM; Supply Voltage VDD = 3.3 V +/-5%
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS NOTES
Operating Supply Current
IDD3.3OP
All outputs active @100MHz, CL = Full load;
427
500
mA
1
Powerdown Current
IDD3.3PDZ
All differential pairs tri-stated
32
40
mA
1
1Guaranteed by design and characterization, not 100% tested in production.
相關(guān)PDF資料
PDF描述
9DB1933AKLFT 9DB SERIES, PLL BASED CLOCK DRIVER, 19 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQCC72
9DB202CGLF 9DB SERIES, PLL BASED CLOCK DRIVER, 2 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO20
9DB202CFLF 9DB SERIES, PLL BASED CLOCK DRIVER, 2 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO20
9DB202CFLFT 9DB SERIES, PLL BASED CLOCK DRIVER, 2 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO20
9DB202CK-01T 9DB SERIES, PLL BASED CLOCK DRIVER, 1 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), QCC32
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
9DB1933AKLFT 功能描述:時鐘緩沖器 19 OUTPUT PCIE GEN3 BUFFER RoHS:否 制造商:Texas Instruments 輸出端數(shù)量:5 最大輸入頻率:40 MHz 傳播延遲（最大值）: 電源電壓-最大:3.45 V 電源電壓-最小:2.375 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LLP-24 封裝:Reel
9DB202CF 制造商:Integrated Device Technology Inc 功能描述:9DB202CF - Rail/Tube
9DB202CFLF 功能描述:時鐘合成器/抖動清除器 2 HCSL Output PCIe Buffer RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel
9DB202CFLFT 功能描述:時鐘緩沖器 2 HCSL Output PCIe Buffer RoHS:否 制造商:Texas Instruments 輸出端數(shù)量:5 最大輸入頻率:40 MHz 傳播延遲（最大值）: 電源電壓-最大:3.45 V 電源電壓-最小:2.375 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LLP-24 封裝:Reel
9DB202CFT 制造商:Integrated Device Technology Inc 功能描述:9DB202CFT - Tape and Reel
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