參數(shù)資料
型號(hào): 9DB1933AKLF
廠商: INTEGRATED DEVICE TECHNOLOGY INC
元件分類: 時(shí)鐘及定時(shí)
英文描述: 9DB SERIES, PLL BASED CLOCK DRIVER, 19 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQCC72
封裝: ROHS COMPLIANT, PLASTIC, QFN-72
文件頁數(shù): 16/17頁
文件大?。?/td> 174K
代理商: 9DB1933AKLF
IDT
Nineteen Output Differential Buffer for PCIe Gen3
9DB1933
Nineteen Output Differential Buffer for PCIe Gen3
8
1676A—07/12/10
Electrical Characteristics - PCIe Phase Jitter Parameters
TA = TCOM; Supply Voltage VDD = 3.3 V +/-5%
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Notes
tjphPCIeG1
PCIe Gen 1
44
86
ps (p-p)
1,2,3
PCIe Gen 2 Lo Band
10kHz < f < 1.5MHz
1.4
3
ps
(rms)
1,2
PCIe Gen 2 High Band
1.5MHz < f < Nyquist (50MHz)
2.5
3.1
ps
(rms)
1,2
tjphPCIeG3
PCIe Gen 3
(PLL BW of 2-4MHz, CDR = 10MHz)
0.6
1
ps
(rms)
1,2,4
tjphPCIeG1
PCIe Gen 1
3
5
ps (p-p)
1,2,3
PCIe Gen 2 Lo Band
10kHz < f < 1.5MHz
0.02
0.1
ps
(rms)
1,2
PCIe Gen 2 High Band
1.5MHz < f < Nyquist (50MHz)
0.2
0.3
ps
(rms)
1,2
tjphPCIeG3
PCIe Gen 3
(PLL BW of 2-4MHz, CDR = 10MHz)
0.04
0.1
ps
(rms)
1,2,4
1 Applies to all outputs.
4 Subject to final radification by PCI SIG.
tjphPCIeG2
2 See http://www.pcisig.com for complete specs
tjphPCIeG2
Phase Jitter, PLL Mode
Additive Phase Jitter,
Bypass Mode
3 Sample size of at least 100K cycles. This figures extrapolates to 108ps pk-pk @ 1M cycles for a BER of 1-12.
相關(guān)PDF資料
PDF描述
9DB1933AKLFT 9DB SERIES, PLL BASED CLOCK DRIVER, 19 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQCC72
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