參數(shù)資料
型號: 9DB401CGLFT
廠商: INTEGRATED DEVICE TECHNOLOGY INC
元件分類: 時鐘及定時
英文描述: 9DB SERIES, PLL BASED CLOCK DRIVER, 4 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO28
封裝: 4.40 MM, 0.65 MM PITCH, ROHS COMPLIANT, MO-153, TSSOP-28
文件頁數(shù): 11/17頁
文件大?。?/td> 160K
代理商: 9DB401CGLFT
IDT
Four Output Differential Buffer for PCI Express
9DB401C
REV H 01/27/11
9DB401C
Four Output Differential Buffer for PCI Express
3
Pin Description for OE_INV = 0
PIN #
PIN NAME
PIN TYPE
DESCRIPTION
1
VDD
PWR
Power supply, nominal 3.3V
2
SRC_IN
IN
0.7 V Differential SRC TRUE input
3
SRC_IN#
IN
0.7 V Differential SRC COMPLEMENTARY input
4
GND
PWR
Ground pin.
5
VDD
PWR
Power supply, nominal 3.3V
6
DIF_1
OUT
0.7V differential true clock output
7
DIF_1#
OUT
0.7V differential complement clock output
8OE_1
IN
Active high input for enabling output 1.
0 = tri-state outputs, 1= enable outputs
9
DIF_2
OUT
0.7V differential true clock output
10
DIF_2#
OUT
0.7V differential complement clock output
11
VDD
PWR
Power supply, nominal 3.3V
12
BYPASS#/PLL
IN
Input to select Bypass(fan-out) or PLL (ZDB) mode
0 = Bypass mode, 1= PLL mode
13
SCLK
IN
Clock pin of SMBus circuitry, 5V tolerant.
14
SDATA
I/O
Data pin for SMBus circuitry, 5V tolerant.
15
PD#
IN
Asynchronous active low input pin used to power down the device.
The internal clocks are disabled and the VCO and the crystal are
stopped.
16
SRC_STOP#
IN
Active low input to stop SRC outputs.
17
HIGH_BW#
IN
3.3V input for selecting PLL Band Width
0 = High, 1= Low
18
VDD
PWR
Power supply, nominal 3.3V
19
DIF_5#
OUT
0.7V differential complement clock output
20
DIF_5
OUT
0.7V differential true clock output
21
OE_6
IN
Active high input for enabling output 6.
0 = tri-state outputs, 1= enable outputs
22
DIF_6#
OUT
0.7V differential complement clock output
23
DIF_6
OUT
0.7V differential true clock output
24
VDD
PWR
Power supply, nominal 3.3V
25
OE_INV
IN
This latched input selects the polarity of the OE pins.
0 = OE pins active high, 1 = OE pins active low (OE#)
26
IREF
OUT
This pin establishes the reference current for the differential current-
mode output pairs. This pin requires a fixed precision resistor tied
to ground in order to establish the appropriate current. 475 ohms is
the standard value.
27
GNDA
PWR
Ground pin for the PLL core.
28
VDDA
PWR
3.3V power for the PLL core.
相關(guān)PDF資料
PDF描述
9DB401CFLF 9DB SERIES, PLL BASED CLOCK DRIVER, 4 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO28
9DB403DGILFT 9DB SERIES, PLL BASED CLOCK DRIVER, 4 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO28
9DB403DFILFT 9DB SERIES, PLL BASED CLOCK DRIVER, 4 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO28
9DB403DFILF 9DB SERIES, PLL BASED CLOCK DRIVER, 4 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO28
9DB403DGLF 9DB SERIES, PLL BASED CLOCK DRIVER, 4 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO28
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