參數(shù)資料
型號(hào)： 9E4101YFILFT
廠商： INTEGRATED DEVICE TECHNOLOGY INC
元件分類： 微控制器/微處理器
英文描述： MICROCONTROLLER, PDSO56
封裝： 0.300 INCH, 0.250 INCH PITCH, ROHS COMPLIANT, MO-118, SSOP-56
文件頁(yè)數(shù)： 16/19頁(yè)
文件大?。?/td> 188K
代理商： 9E4101YFILFT
IDTTM
Programmable Timing Control HubTM for Intel Systems
1408A—01/25/10
ICS9E4101
Programmable Timing Control HubTM for Intel Systems
6
I
2C Table: Read-Back Register
Pin #
Name
Control Function
Type0
1
PWD
Bit 7
CPUCLK2/RCCLK7 Enable
Output Enable
RW
DISABLE
ENABLE
1
Bit 6
SRCCLK6 Enable
Output Enable
RW
DISABLE
ENABLE
1
Bit 5
SRCCLK5 Enable
Output Enable
RW
DISABLE
ENABLE
1
Bit 4
SRCCLK4 Enable
Output Enable
RW
DISABLE
ENABLE
1
Bit 3
SRCCLK3 Enable
Output Enable
RW
DISABLE
ENABLE
1
Bit 2
SRCCLK2 Enable
Output Enable
RW
DISABLE
ENABLE
1
Bit 1
SRCCLK1 Enable
Output Enable
RW
DISABLE
ENABLE
1
Bit 0
I
2C Table: Spreading and Device Behavior Control Register
Pin #
Name
Control Function
Type0
1
PWD
Bit 7
PCI_F0 Enable
Output Enable
RW
Disable
Enable
1
Bit 6
DOT_96MHz
Output Enable
RW
Disable
Enable
1
Bit 5
USB_48MHz Enable
Output Enable
RW
Disable
Enable
1
Bit 4
REFOUT Enable
Output Enable
RW
Disable
Enable
1
Bit 3
1
Bit 2
CPUT1/CPUC1
Output Enable
RW
Disable
Enable
1
Bit 1
CPUT0/CPUC0
Output Enable
RW
Disable
Enable
1
Bit 0
Spread Spectrum Mode
Spread Off
RW
SPREAD OFF
SPREAD
ON
0
I
2C Table: Output Control Register
Pin #
Name
Control Function
Type0
1
PWD
Bit 7
PCICLK5
Output Enable
RW
Disable
Enable
1
Bit 6
PCICLK4
Output Enable
RW
Disable
Enable
1
Bit 5
PCICLK3
Output Enable
RW
Disable
Enable
1
Bit 4
PCICLK2
Output Enable
RW
Disable
Enable
1
Bit 3
PCICLK1
Output Enable
RW
Disable
Enable
1
Bit 2
PCICLK0
Output Enable
RW
Disable
Enable
1
Bit 1
PCI_F2 Enable
Output Enable
RW
Disable
Enable
1
Bit 0
PCI_F1 Enable
Output Enable
RW
Disable
Enable
1
I
2C Table: Output Control Register
Pin #
Name
Control Function
Type0
1
PWD
Bit 7
CPU_ITP/SRCCLK7
RW
Free-Running
Stoppable
0
Bit 6
SRCCLK6
RW
Free-Running
Stoppable
0
Bit 5
SRCCLK5
RW
Free-Running
Stoppable
0
Bit 4
SRCCLK4
RW
Free-Running
Stoppable
0
Bit 3
SRCCLK3
RW
Free-Running
Stoppable
0
Bit 2
SRCCLK2
RW
Free-Running
Stoppable
0
Bit 1
SRCCLK1
RW
Free-Running
Stoppable
0
Bit 0
0
I
2C Table: Output Control Register
Pin #
Name
Control Function
Type0
1
PWD
Bit 7
1
Bit 6
DOT_96MHz
Driven in PD
RW
Driven
Hi-Z
1
Bit 5
PCI_F2
RW
Free-Running
Stoppable
1
Bit 4
PCI_F1
RW
Free-Running
Stoppable
1
Bit 3
PCI_F0
RW
Free-Running
Stoppable
1
Bit 2
1
Bit 1
1
Bit 0
1
Free-Running
Control
default:
not affected by
PCI/SRC_STOP
(Byte 6, bit 3)
RESERVED
-
Byte 1
54
14,15
RESERVED
35,35
12
52
14,15
Byte 3
43,44
-
40,41
Byte 2
5
10
RESERVED
24,25
22,23
19,20
Byte 4
-
26,27
24,25
22,23
19,20
Byte 0
35,36
32,33
30,31
10
9
8
RESERVED
Free-Running
Control
not affected by
RESERVED
4
3
56
55
30,31
26,27
32,33
9
54
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