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參數(shù)資料
| 型號： | 9FG107AG |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時鐘產(chǎn)生/分配 |
| 英文描述： | 400 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO48 |
| 封裝： | 6.10 MM, 0.50 MM PITCH, GREEN, MO-153, TSSOP-48 |
| 文件頁數(shù)： | 10/16頁 |
| 文件大?。?/td> | 191K |
| 代理商： | 9FG107AG |
3
Integrated
Circuit
Systems, Inc.
ICS9FG107
0863C—11/22/04
Pin Description (Continued)
PIN
#
PIN NAME
PIN TYPE
DESCRIPTION
25
DIF_STOP#
IN
Active low input to stop differential output clocks.
26
*SPREAD
IN
Asynchronous, active high input, with internal 120Kohm pull-up
resistor, to enable spread spectrum functionality.
27
**SEL14M_25M#
IN
Select 14.31818 MHz or 25 Mhz input frequency. 1 = 14.31818 MHz,
0 = 25 MHz
28
*OE_3
IN
Active high input for enabling outputs.
0 = tri-state outputs, 1= enable outputs
29
DIF_3#
OUT
0.7V differential complement clock outputs
30
DIF_3
OUT
0.7V differential true clock outputs
31
VDD
PWR
Power supply, nominal 3.3V
32
DIF_2#
OUT
0.7V differential complement clock outputs
33
DIF_2
OUT
0.7V differential true clock outputs
34
**OE_2
IN
Active high input for enabling outputs.
0 = tri-state outputs, 1= enable outputs
35
GND
PWR
Ground pin.
36
VDD
PWR
Power supply, nominal 3.3V
37
**OE_1
IN
Active high input for enabling outputs.
0 = tri-state outputs, 1= enable outputs
38
DIF_1#
OUT
0.7V differential complement clock outputs
39
DIF_1
OUT
0.7V differential true clock outputs
40
VDD
PWR
Power supply, nominal 3.3V
41
DIF_0#
OUT
0.7V differential complement clock outputs
42
DIF_0
OUT
0.7V differential true clock outputs
43
*OE_0
IN
Active high input for enabling outputs.
0 = tri-state outputs, 1= enable outputs
44
**FS1
I/O
Frequency select latch input pin / 3.3V 66.66MHz clock output.
45
*DWNSPRD#
IN
3.3V input that selects spread mode. This input is not latched at
power up.
0 = Down Spread, 1 = Center Spread
46
IREF
OUT
This pin establishes the reference current for the differential current-
mode output pairs. This pin requires a fixed precision resistor tied to
ground in order to establish the appropriate current. 475 ohms is the
standard value.
47
GNDA
PWR
Ground pin for the PLL core.
48
VDDA
PWR
3.3V power for the PLL core.
Pins preceeded by * have 120 Kohm pull DOWN resistors
Pins preceeded by ** have 120 Kohm pull UP resistors
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| 9FG108CFLFT | 400 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO48 |
| 9FG108CFLF | 400 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO48 |
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| 9FG108DFILF | 400 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO48 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 9FG107AGLNT | 功能描述:時鐘合成器/抖動清除器 RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel |
| 9FG108CFLF | 制造商:Integrated Device Technology Inc 功能描述:IDT 9FG108CFLF PHASED LOCKED LOOP (PLL) - Tape and Reel 制造商:Integrated Device Technology Inc 功能描述:IDT 9FG108CFLF Phased Locked Loop (PLL) |
| 9FG108DFILF | 功能描述:時鐘合成器/抖動清除器 PCIE GEN2 SYNTHESIZER RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel |
| 9FG108DFILFT | 功能描述:時鐘合成器/抖動清除器 PCIE GEN2 SYNTHESIZER RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel |
| 9FG108DFLF | 功能描述:時鐘合成器/抖動清除器 PCIE GEN2 SYNTHESIZER RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel |
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