- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄25566 > 9FG107AGLN (INTEGRATED DEVICE TECHNOLOGY INC) 400 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO48 PDF資料下載
參數(shù)資料
| 型號： | 9FG107AGLN |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時鐘產(chǎn)生/分配 |
| 英文描述： | 400 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO48 |
| 封裝： | 6.10 MM, 0.50 MM PITCH, GREEN, MO-153, TSSOP-48 |
| 文件頁數(shù)： | 12/16頁 |
| 文件大小： | 191K |
| 代理商： | 9FG107AGLN |
5
Integrated
Circuit
Systems, Inc.
ICS9FG107
0863C—11/22/04
Absolute Max
Symbol
Parameter
Min
Max
Units
VDD_A
3.3V Core Supply Voltage
VDD + 0.5V
V
VDD_In
3.3V Logic Input Supply Voltage
GND - 0.5
VDD + 0.5V
V
Ts
Storage Temperature
-65
150
°C
Tambient
Ambient Operating Temp
0
70
°C
Tcase
Case Temperature
115
°C
ESD prot
Input ESD protection
human body model
2000
V
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70°C; Supply Voltage VDD = 3.3 V +/-5%
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS NOTES
Input High Voltage
VIH
3.3 V +/-5%
2
VDD + 0.3
V
Input Low Voltage
VIL
3.3 V +/-5%
VSS - 0.3
0.8
V
Input High Current
IIH
VIN = VDD
-5
5
uA
IIL1
VIN = 0 V; Inputs with no pull-
up resistors
-5
uA
IIL2
VIN = 0 V; Inputs with pull-up
resistors
-200
uA
Full Active, CL = Full load;
f = 400 MHz
250
mA
Full Active, CL = Full load;
f = 100 MHz
200
mA
Input Frequency
3
Fi
VDD = 3.3 V
14
25
MHz
3
Pin Inductance
1
Lpin
7nH
1
CIN
Logic Inputs
1.5
5
pF
1
COUT
Output pin capacitance
6
pF
1
Clk Stabilization
1,2
TSTAB
From VDD Power-Up and after
input clock stabilization to 1st
clock
1.8
ms
1,2
Modulation Frequency
fMOD
Triangular Modulation
30
40
kHz
1
DIF output enable
tDIFOE
DIF output enable after
DIF_Stop# de-assertion
10
ns
1
Input Rise and Fall times
tR/tF
20% to 80% of VDD
5
ns
1
1Guaranteed by design and characterization, not 100% tested in production.
2See timing diagrams for timing requirements.
3 Input frequency should be measured at the REFOUT pin and tuned to ideal 14.31818MHz or 25 MHz to meet
ppm frequency accuracy on PLL outputs.
Input/Output
Capacitance
1
Input Low Current
IDD3.3OP
Operating Supply Current
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| 9FG107AG | 400 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO48 |
| 9FG108CFLFT | 400 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO48 |
| 9FG108CFLF | 400 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO48 |
| 9FG108CGLFT | 400 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO48 |
| 9FG108DFLF | 400 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO48 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 9FG107AGLNT | 功能描述:時鐘合成器/抖動清除器 RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel |
| 9FG108CFLF | 制造商:Integrated Device Technology Inc 功能描述:IDT 9FG108CFLF PHASED LOCKED LOOP (PLL) - Tape and Reel 制造商:Integrated Device Technology Inc 功能描述:IDT 9FG108CFLF Phased Locked Loop (PLL) |
| 9FG108DFILF | 功能描述:時鐘合成器/抖動清除器 PCIE GEN2 SYNTHESIZER RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel |
| 9FG108DFILFT | 功能描述:時鐘合成器/抖動清除器 PCIE GEN2 SYNTHESIZER RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel |
| 9FG108DFLF | 功能描述:時鐘合成器/抖動清除器 PCIE GEN2 SYNTHESIZER RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。