參數(shù)資料
型號(hào): 9FG1200DF-1LF
廠商: INTEGRATED DEVICE TECHNOLOGY INC
元件分類: 時(shí)鐘產(chǎn)生/分配
英文描述: 400 MHz, OTHER CLOCK GENERATOR, PDSO56
封裝: 0.300 INCH, 0.025 INCH PITCH, ROHS COMPLIANT, MO-118, SSOP-56
文件頁數(shù): 7/23頁
文件大?。?/td> 188K
代理商: 9FG1200DF-1LF
IDT
Frequency Gearing Clock for CPU, PCIe Gen1, Gen2 & FBD
1138C
02/08/10
ICS9FG1200D-1
15
SMBusTable: 1:1 PLL Frequency Selection
Pin #
Name
Control Function
Type0
1
PWD
Bit 7
0
Bit 6
0
Bit 5
0
Bit 4
0
Bit 3
0
Bit 2
RW
x
Bit 1
RW
1
Bit 0
RW
Latch
SMBusTable: Reserved Register
Pin #
Name
Control Function
Type0
1
PWD
Bit 7
0
Bit 6
0
Bit 5
0
Bit 4
0
Bit 3
0
Bit 2
0
Bit 1
0
Bit 0
0
SMBus Table: M/N Programming Enable
Pin #
Name
Control Function
Type0
1
PWD
Bit 7
M/N_EN
Gear PLL and 1:1 PLL
M/N Programming
Enable
RW
Disable
Enable
0
Bit 6
X
Bit 5
X
Bit 4
X
Bit 3
X
Bit 2
X
Bit 1
X
Bit 0
X
SMBus Table: Gear PLL Frequency Control Register
Pin #
Name
Control Function
Type0
1
PWD
Bit 7
X
Bit 6
X
Bit 5
Gear PLL M Div5
RW
X
Bit 4
Gear PLL M Div4
RW
X
Bit 3
Gear PLL M Div3
RW
X
Bit 2
Gear PLL M Div2
RW
X
Bit 1
Gear PLL M Div1
RW
X
Bit 0
Gear PLL M Div0
RW
X
Byte 9
RESERVED
Byte 10
-
Byte 11
M Divider Programming
bits
-
Byte 8
-
RESERVED
Frequency Select C
Frequency Select B
FS_A_410
RESERVED
See 9FG1200-1 1:1 PLL
Programming Table
RESERVED
Contact IDT for 9FG1200-
1 M/N programming Table
RESERVED
相關(guān)PDF資料
PDF描述
9FG1200YG-1LF-T 400 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO56
9FG1200YF-1LF-T 400 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO56
9FG1201HGLF-T 400 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO56
9FG1201HGLF 400 MHz, OTHER CLOCK GENERATOR, PDSO56
9FG1201HGLFT 400 MHz, OTHER CLOCK GENERATOR, PDSO56
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