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參數(shù)資料
| 型號： | 9FG1201HGLFT |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時鐘產(chǎn)生/分配 |
| 英文描述： | 400 MHz, OTHER CLOCK GENERATOR, PDSO56 |
| 封裝： | 6.10 MM, 0.50 PITCH, ROHS COMPLIANT, MO-153, TSSOP-56 |
| 文件頁數(shù)： | 23/23頁 |
| 文件大?。?/td> | 268K |
| 代理商： | 9FG1201HGLFT |
IDTTM/ICSTM
Frequency Gearing Clock for CPU, PCIe Gen1, Gen2, & FBD
1371F — 09/23/09
ICS9FG1201H
Frequency Gearing Clock for CPU, PCIe Gen1, Gen2, & FBD
9
SMBusTable: Gear Ratio Select Register
Pin #
Name
Control Function
Type0
1
PWD
Bit 7
RW
Gear Ratio
1:1
1
Bit 6
RW
Gear Ratio
1:1
1
Bit 5
RW
1
Bit 4
RW
Latch
Bit 3
RW
1
Bit 2
RW
0
Bit 1
RW
1
Bit 0
RW
1
SMBusTable: Output Control Register
Pin #
Name
Control Function
Type0
1
PWD
Bit 7
DIF_7
Output Control
RW
Hi-Z
Enable
1
Bit 6
DIF_6
Output Control
RW
Hi-Z
Enable
1
Bit 5
DIF_5
Output Control
RW
Hi-Z
Enable
1
Bit 4
DIF_4
Output Control
RW
Hi-Z
Enable
1
Bit 3
DIF_3
Output Control
RW
Hi-Z
Enable
1
Bit 2
DIF_2
Output Control
RW
Hi-Z
Enable
1
Bit 1
DIF_1
Output Control
RW
Hi-Z
Enable
1
Bit 0
DIF_0
Output Control
RW
Hi-Z
Enable
1
SMBusTable: Output and PLL BW Control Register
Pin #
Name
Control Function
Type0
1
PWD
Bit 7
1
Bit 6
RW
High BW
Low BW
1
Bit 5
RW
Bypass
PLL
1
Bit 4
1
Bit 3
DIF_11
Output Control
RW
Hi-Z
Enable
1
Bit 2
DIF_10
Output Control
RW
Hi-Z
Enable
1
Bit 1
DIF_9
Output Control
RW
Hi-Z
Enable
1
Bit 0
DIF_8
Output Control
RW
Hi-Z
Enable
1
Note: Bit 6 is wired OR to the pin 1 input, any 0 selects High BW
Note: Bit 5 is wired OR to the pin 30 input, any 0 selects Fanout Bypass mode
SMBusTable: Output Enable Readback Register
Pin #
Name
Control Function
Type0
1
PWD
Bit 7
R
X
Bit 6
R
X
Bit 5
R
X
Bit 4
R
X
Bit 3
R
X
Bit 2
R
X
Bit 1
R
X
Bit 0
R
X
Byte 3
Readback - OE7# Input
Readback
Readback - OE1# Input
Readback
see note
PLL_BW# adjust
see note
51,52
47,48
31
Readback - OE6# Input
Readback - OE3# Input
Readback - OE5# Input
Readback - OE4# Input
Readback - OE2# Input
5
Readback - OE0# Input
16,17
13,14
9,10
6,7
See 9FG1201
Programmable Gear
Ratios Table
-Gear Ratio FS3
-Gear Ratio FS2
-Gear Ratio FS1
-Gear Ratio FS0
Group of 10 gear ratio enable
DIF(11:10)
Group of 2 gear ratio enable
-
Gear Ratio FS4 (FS_A_410)
-Reserved
Byte 0
DIF(9:0)
Byte 1
35, 36
32, 33
24, 25
19,20
34
26
21
18
8
15
Readback
Byte 2
Reserved
39,40
Readback
BYPASS# test mode / PLL
42,43
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