參數(shù)資料
型號: 9FG1201HGLFT
廠商: INTEGRATED DEVICE TECHNOLOGY INC
元件分類: 時鐘產(chǎn)生/分配
英文描述: 400 MHz, OTHER CLOCK GENERATOR, PDSO56
封裝: 6.10 MM, 0.50 PITCH, ROHS COMPLIANT, MO-153, TSSOP-56
文件頁數(shù): 4/23頁
文件大?。?/td> 268K
代理商: 9FG1201HGLFT
IDTTM/ICSTM
Frequency Gearing Clock for CPU, PCIe Gen1, Gen2, & FBD
1371F — 09/23/09
ICS9FG1201H
Frequency Gearing Clock for CPU, PCIe Gen1, Gen2, & FBD
12
SMBus Table: Gear PLL Frequency Control Register
Pin #
Name
Control Function
Type0
1
PWD
Bit 7
Gear PLL N Div7
RW
X
Bit 6
Gear PLL N Div6
RW
X
Bit 5
Gear PLL N Div5
RW
X
Bit 4
Gear PLL N Div4
RW
X
Bit 3
Gear PLL N Div3
RW
X
Bit 2
Gear PLL N Div2
RW
X
Bit 1
Gear PLL N Div1
RW
X
Bit 0
Gear PLL N Div0
RW
X
SMBusTable: Gear PLL Output Divider Register
Pin #
Name
Control Function
Type0
1
PWD
Bit 7
0
Bit 6
0
Bit 5
0
Bit 4
0
Bit 3
GoutDiv 3
RW
X
Bit 2
GoutDiv 2
RW
X
Bit 1
GoutDiv 1
RW
X
Bit 0
GoutDiv 1
RW
X
SMBusTable: Reserved Register
Pin #
Name
Control Function
Type0
1
PWD
Bit 7
0
Bit 6
0
Bit 5
0
Bit 4
0
Bit 3
0
Bit 2
0
Bit 1
0
Bit 0
0
SMBusTable: Reserved Register
Pin #
Name
Control Function
Type0
1
PWD
Bit 7
0
Bit 6
0
Bit 5
0
Bit 4
0
Bit 3
0
Bit 2
0
Bit 1
0
Bit 0
0
RESERVED
Byte 15
Byte 13
Byte 14
-
RESERVED
See Gear Output Divider
Table
Gear Output Divider
RESERVED
N Divider Programming
bits
RESERVED
See 9FG1201H M/N
programming Table
RESERVED
-
Byte 12
-
RESERVED
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