參數(shù)資料
型號: 9FG1901YK-T
廠商: INTEGRATED DEVICE TECHNOLOGY INC
元件分類: 時鐘產(chǎn)生/分配
英文描述: 400 MHz, PROC SPECIFIC CLOCK GENERATOR, PQCC72
封裝: PLASTIC, MO-220, MLF-72
文件頁數(shù): 4/17頁
文件大?。?/td> 233K
代理商: 9FG1901YK-T
12
Integrated
Circuit
Systems, Inc.
ICS9FG1901
0962E—01/02/07
SMBusTable: Control Pin Readback Register
Pin #
Name
Control Function
Type0
1
PWD
Bit 7
R
X
Bit 6
X
Bit 5
X
Bit 4
DIF_18
Output Control
RW
Hi-Z
Enable
1
Bit 3
DIF_17
Output Control
RW
Hi-Z
Enable
1
Bit 2
DIF_16
Output Control
RW
Hi-Z
Enable
1
Bit 1
DIF_15
Output Control
RW
Hi-Z
Enable
1
Bit 0
DIF_14
Output Control
RW
Hi-Z
Enable
1
SMBusTable: Reserved Register
Pin #
Name
Control Function
Type0
1
PWD
Bit 7
0
Bit 6
0
Bit 5
0
Bit 4
0
Bit 3
0
Bit 2
0
Bit 1
0
Bit 0
0
SMBus Table: M/N Programming & Watchdog Safe Register
Pin #
Name
Control Function
Type0
1
PWD
Bit 7
M/N_EN
Gearing PLL and 1:1 PLL M/N
Programming Enable
RW
Disable
Enable
0
Bit 6
X
Bit 5
X
Bit 4
X
Bit 3
X
Bit 2
X
Bit 1
X
Bit 0
X
SMBus Table: Gearing PLL Frequency Control Register
Pin #
Name
Control Function
Type0
1
PWD
Bit 7
Gearing PLL N Div8
N Divider Prog bit 8
RW
X
Bit 6
Gearing PLL N Div9
N Divider Prog bit 9
RW
X
Bit 5
Gearing PLL M Div5
RW
X
Bit 4
Gearing PLL M Div4
RW
X
Bit 3
Gearing PLL M Div3
RW
X
Bit 2
Gearing PLL M Div2
RW
X
Bit 1
Gearing PLL M Div1
RW
X
Bit 0
Gearing PLL M Div0
RW
X
RESERVED
Byte 9
Byte 8
RESERVED
-
M Divider Programming
bit (5:0)
-
Byte 11
-
Byte 10
-
RESERVED
5
Readback - FS_A_410
Readback
RESERVED
相關(guān)PDF資料
PDF描述
9FG430AGILFT 400 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO28
9FG430AGLF 400 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO28
9FG430AFILF 400 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO28
9FG430AGLFT 400 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO28
9FG430AGILF 400 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO28
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