- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄25566 > 9FG1901YKLF-T (INTEGRATED DEVICE TECHNOLOGY INC) 400 MHz, PROC SPECIFIC CLOCK GENERATOR, PQCC72 PDF資料下載
參數(shù)資料
| 型號(hào)： | 9FG1901YKLF-T |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時(shí)鐘產(chǎn)生/分配 |
| 英文描述： | 400 MHz, PROC SPECIFIC CLOCK GENERATOR, PQCC72 |
| 封裝： | ROHS COMPLIANT, PLASTIC, MO-220, MLF-72 |
| 文件頁數(shù)： | 16/17頁 |
| 文件大小： | 233K |
| 代理商： | 9FG1901YKLF-T |
8
Integrated
Circuit
Systems, Inc.
ICS9FG1901
0962E—01/02/07
PLL Bandwidth and Peaking
Parameter
Conditions
Min
Typical
Max
Units
Notes
PLL Jitter Peaking
jpeak-hibw
(HIGH_BW# = 0)
0
1
2.5
dB
2,8
PLL Jitter Peaking
jpeak-lobw
(HIGH_BW# = 1)
0
1
2
dB
2,8
PLL Bandwidth
pllHIBW
(HIGH_BW# = 0)
2
2.3
4
MHz
1,8
PLL Bandwidth
pllLOBW
(HIGH_BW# = 1)
0.7
1.28
1.4
MHz
1,8
Output phase jitter impact – PCIe*
Gen1
θPCIe1
(including PLL BW 1.5-22 MHz, z = 0.54,
Td=10 ns, Ftrk=1.5 MHz )
0
77
108
ps
3,6,7,8
Output phase jitter impact – FBD
θFBD
(including PLL BW 11- 33 Mz, z = 0.54,
Td=5 ns, Ftrk=0.2 MHz)
0
3
ps RMS 3,4,7,8
NOTES:
1.
Measured at 3 db down or half power point.
2.
Measured as maximum pass band gain. At frequencies within the loop BW, highest point of magnification is called PLL jitter peaking.
3.
Post processed evaluation through Intel supplied Matlab scripts.
4.
Refer to FB-DIMM Specification: “High Speed Differential Point-to-Point Link at 1.5 V” for updates to this specification.
6.
These jitter numbers are defined for a BER of 1E-12. Measured numbers at a smaller sample size have to be extrapolated to this BER target.
7.
z
= 0.54 is implying a jitter peaking of 3 dB.
8. Guaranteed by design and characterization, not 100% tested in production.
5.
PCIe* Gen2 filter characteristics are subject to final ratification by PC ISIG. Please check the PCI* SIG for the latest specification. Tested with DBxx00G driven by low phase
noise signal generator such as an Agilent 8133A.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| 9FG1901YK-T | 400 MHz, PROC SPECIFIC CLOCK GENERATOR, PQCC72 |
| 9FG430AGILFT | 400 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO28 |
| 9FG430AGLF | 400 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO28 |
| 9FG430AFILF | 400 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO28 |
| 9FG430AGLFT | 400 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO28 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 9FG1902AKLF | 制造商:Integrated Device Technology Inc 功能描述:PCIE BUFFER 制造商:Integrated Device Technology Inc 功能描述:72 VFQFN (LEAD FREE) - Rail/Tube |
| 9FG1902AKLFT | 制造商:Integrated Device Technology Inc 功能描述:PCIE BUFFER 制造商:Integrated Device Technology Inc 功能描述:72 VFQFN (LEAD FREE) - Tape and Reel |
| 9FG1903AK-1LF | 制造商:Integrated Device Technology Inc 功能描述:PCIE BUFFER 制造商:Integrated Device Technology Inc 功能描述:72 VFQFN (LEAD FREE) - Rail/Tube |
| 9FG1903AK-1LFT | 功能描述:時(shí)鐘緩沖器 PCIE BUFFER RoHS:否 制造商:Texas Instruments 輸出端數(shù)量:5 最大輸入頻率:40 MHz 傳播延遲（最大值）: 電源電壓-最大:3.45 V 電源電壓-最小:2.375 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LLP-24 封裝:Reel |
| 9FG1903AKLF | 功能描述:時(shí)鐘緩沖器 PCIE BUFFER RoHS:否 制造商:Texas Instruments 輸出端數(shù)量:5 最大輸入頻率:40 MHz 傳播延遲（最大值）: 電源電壓-最大:3.45 V 電源電壓-最小:2.375 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LLP-24 封裝:Reel |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。