參數(shù)資料
型號: 9FG1901YKLF-T
廠商: INTEGRATED DEVICE TECHNOLOGY INC
元件分類: 時鐘產(chǎn)生/分配
英文描述: 400 MHz, PROC SPECIFIC CLOCK GENERATOR, PQCC72
封裝: ROHS COMPLIANT, PLASTIC, MO-220, MLF-72
文件頁數(shù): 5/17頁
文件大?。?/td> 233K
代理商: 9FG1901YKLF-T
13
Integrated
Circuit
Systems, Inc.
ICS9FG1901
0962E—01/02/07
SMBus Table: Gearing PLL Frequency Control Register
Pin #
Name
Control Function
Type0
1
PWD
Bit 7
Gearing PLL N Div7
RW
X
Bit 6
Gearing PLL N Div6
RW
X
Bit 5
Gearing PLL N Div5
RW
X
Bit 4
Gearing PLL N Div4
RW
X
Bit 3
Gearing PLL N Div3
RW
X
Bit 2
Gearing PLL N Div2
RW
X
Bit 1
Gearing PLL N Div1
RW
X
Bit 0
Gearing PLL N Div0
RW
X
SMBusTable: Gearing PLL Output Divider Register (Rev H and higher)
Pin #
Name
Control Function
Type0
1
PWD
Bit 7
0
Bit 6
0
Bit 5
0
Bit 4
0
Bit 3
Gearing PLL OutDiv 3
PLL 1 Output Divider
RW
X
Bit 2
Gearing PLL OutDiv 2
PLL 1 Output Divider
RW
X
Bit 1
Gearing PLL OutDiv 1
PLL 1 Output Divider
RW
X
Bit 0
Gearing PLL OutDiv 0
PLL 1 Output Divider
RW
X
SMBusTable: Reserved Register
Pin #
Name
Control Function
Type0
1
PWD
Bit 7
0
Bit 6
0
Bit 5
0
Bit 4
0
Bit 3
0
Bit 2
0
Bit 1
0
Bit 0
0
SMBusTable: Reserved Register
Pin #
Name
Control Function
Type0
1
PWD
Bit 7
0
Bit 6
0
Bit 5
0
Bit 4
0
Bit 3
0
Bit 2
0
Bit 1
0
Bit 0
0
RESERVED
Byte 15
RESERVED
See Output Divider Table
Byte 14
RESERVED
-
Byte 13
RESERVED
Byte 12
-
N Divider Programming
Byte12 bit(7:0) and Byte11
bit(7:6)
-
RESERVED
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