參數(shù)資料
型號: 9S12DP256BDGV2
英文描述: 9S12Dx256B Device Guide. also covers C derivatives and 9S12Ax256 devices
中文描述: 9S12Dx256B設(shè)備指南。也包括C衍生物和9S12Ax256設(shè)備
文件頁數(shù): 90/126頁
文件大?。?/td> 1809K
代理商: 9S12DP256BDGV2
MC9S12DJ64 Device User Guide — V01.17
90
The total power dissipation can be calculated from:
Two cases with internal voltage regulator enabled and disabled must be considered:
1.
Internal Voltage Regulator disabled
P
IO
is the sum of all output currents on I/O ports associated with VDDX and VDDR.
For R
DSON
is valid:
VOL
IOL
respectively
2.
Internal voltage regulator enabled
I
DDR
is the current shown in
Table A-7
and not the overall current flowing into VDDR, which
additionally contains the current flowing into the external loads with output high.
i
P
IO
is the sum of all output currents on I/O ports associated with VDDX and VDDR.
TA
PD
Θ
JA
Ambient Temperature, [
°
C
]
=
Total Chip Power Dissipation, [W]
=
Package Thermal Resistance, [
°
C/W]
=
PD
PINT
PIO
+
=
PINT
Chip Internal Power Dissipation, [W]
=
PINT
IDD
VDD
IDDPLL
i
VDDPLL
IDDA
+
VDDA
+
=
PIO
RDSON
IIOi
2
=
RDSON
------------;
=
RDSON
VDD5
----------------------------------- for outputs driven high
;
VOH
IOH
=
PINT
IDDR
VDDR
IDDA
VDDA
+
=
PIO
RDSON
IIOi
2
=
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參數(shù)描述
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