參數(shù)資料
型號(hào): 9S12DT256DGV3
廠商: Motorola, Inc.
英文描述: MC9S12DT256 Device User Guide V03.03
中文描述: MC9S12DT256設(shè)備的用戶手冊V03.03
文件頁數(shù): 119/130頁
文件大?。?/td> 2077K
代理商: 9S12DT256DGV3
MC9S12DT256 Device User Guide — V03.03
117
A.7 SPI
This section provides electrical parametrics and ratings for the SPI.
In
Table A-18
the measurement conditions are listed.
A.7.1 Master Mode
In
Figure A-5
the timing diagram for master mode with transmission format CPHA=0 is depicted.
Figure A-5 SPI Master Timing (CPHA=0)
In
Figure A-6
the timing diagram for master mode with transmission format CPHA=1 is depicted.
Table A-18 Measurement Conditions
Description
Value
Unit
Drive mode
Load capacitance C
LOAD,
on all outputs
Thresholds for delay
measurement points
full drive mode
50
pF
(20% / 80%) VDDX
V
SCK
(OUTPUT)
SCK
(OUTPUT)
MISO
(INPUT)
MOSI
(OUTPUT)
SS
1
(OUTPUT)
1
9
5
6
MSB IN
2
BIT 6 . . . 1
LSB IN
MSB OUT
2
LSB OUT
BIT 6 . . . 1
11
4
4
2
10
(CPOL
=
0)
(CPOL
=
1)
3
13
13
1.if configured as an output.
2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB.
12
12
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