(W or s t - C as e M i l i t a r y Cond i t i o n s , V
參數(shù)資料
型號： A1020B-2PLG84I
廠商： Microsemi SoC
文件頁數(shù)： 27/98頁
文件大?。?/td> 0K
描述： IC FPGA 2K GATES 84-PLCC IND
標(biāo)準包裝： 16
系列： ACT™ 1
LAB/CLB數(shù)： 547
輸入/輸出數(shù)： 69
門數(shù)： 2000
電源電壓： 4.5 V ~ 5.5 V
安裝類型： 表面貼裝
工作溫度： -40°C ~ 85°C
封裝/外殼： 84-LCC（J 形引線）
供應(yīng)商設(shè)備封裝： 84-PLCC（29.31x29.31）
33
Hi R e l F P GA s
A1 28 0XL Ti m i ng Cha r act e r i s t i cs
(W or s t - C as e M i l i t a r y Cond i t i o n s , V CC = 4.5 V, TJ = 1 25°C)
‘–1’ Speed
‘Std’ Speed
Parameter
Description
Min.
Max.
Min.
Max.
Units
Logic Module Propagation Delays1
tPD1
Single Module
3.7
4.3
ns
tCO
Sequential Clk to Q
3.7
4.3
ns
tGO
Latch G to Q
3.7
4.3
ns
tRS
Flip-Flop (Latch) Reset to Q
3.7
4.3
ns
Logic Module Predicted Routing Delays2
tRD1
FO=1 Routing Delay
1.7
2.1
ns
tRD2
FO=2 Routing Delay
2.5
3.0
ns
tRD3
FO=3 Routing Delay
3.1
3.6
ns
tRD4
FO=4 Routing Delay
3.7
4.3
ns
tRD8
FO=8 Routing Delay
7.0
8.3
ns
Logic Module Sequential Timing3, 4
tSUD
Flip-Flop (Latch) Data Input Setup
0.4
0.5
ns
tHD
Flip-Flop (Latch) Data Input Hold
0.0
ns
tSUENA
Flip-Flop (Latch) Enable Setup
1.1
1.2
ns
tHENA
Flip-Flop (Latch) Enable Hold
0.0
ns
tWCLKA
Flip-Flop (Latch) Clock Active Pulse
Width
5.3
6.1
ns
tWASYN
Flip-Flop (Latch) Asynchronous Pulse
Width
5.3
6.1
ns
tA
Flip-Flop Clock Input Period
10.7
12.3
ns
tINH
Input Buffer Latch Hold
0.0
ns
tINSU
Input Buffer Latch Setup
0.4
ns
tOUTH
Output Buffer Latch Hold
0.0
ns
tOUTSU
Output Buffer Latch Setup
0.4
ns
fMAX
Flip-Flop (Latch) Clock Frequency
90
75
MHz
Notes:
1.
For dual-module macros, use tPD1 + tRD1 + tPDn , tCO + tRD1 + tPDn , or tPD1 + tRD1 + tSUD , whichever is appropriate.
2.
Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device
performance. Post-route timing analysis or simulation is required to determine actual worst-case performance. Post-route timing is
based on actual routing delay measurements performed on the device prior to shipment.
3.
Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules can be obtained
from the DirectTime Analyzer utility.
4.
Setup and hold timing parameters for the input buffer latch are defined with respect to the PAD and the D input. External setup/hold
timing parameters must account for delay from an external PAD signal to the G inputs. Delay from an external PAD signal to the G input
subtracts (adds) to the internal setup (hold) time.
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參數(shù)描述
A1020B-2PQ100C 功能描述:IC FPGA 2K GATES 100-PQFP COM RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:ACT™ 1 產(chǎn)品培訓(xùn)模塊:Three Reasons to Use FPGA's in Industrial Designs Cyclone IV FPGA Family Overview 特色產(chǎn)品:Cyclone? IV FPGAs 標(biāo)準包裝:60 系列:CYCLONE® IV GX LAB/CLB數(shù):9360 邏輯元件/單元數(shù):149760 RAM 位總計:6635520 輸入/輸出數(shù):270 門數(shù):- 電源電壓:1.16 V ~ 1.24 V 安裝類型:表面貼裝 工作溫度:0°C ~ 85°C 封裝/外殼:484-BGA 供應(yīng)商設(shè)備封裝:484-FBGA（23x23）
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A1020B-2PQ84I 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:ACT 1 Series FPGAs
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