Table 2-13 A1225A Worst-Case Commercial Conditions" />
參數(shù)資料
型號： A1240A-TQG176C
廠商： Microsemi SoC
文件頁數(shù)： 11/54頁
文件大?。?/td> 0K
描述： IC FPGA 4K GATES 176-TQFP COM
標準包裝： 40
系列： ACT™ 2
LAB/CLB數(shù)： 684
輸入/輸出數(shù)： 104
門數(shù)： 4000
電源電壓： 4.5 V ~ 5.5 V
安裝類型： 表面貼裝
工作溫度： 0°C ~ 70°C
封裝/外殼： 176-LQFP
供應商設備封裝： 176-TQFP（24x24）
ACT 2 Family FPGAs
R e visio n 8
2 - 13
A1225A Timing Characteristics (continued)
Table 2-13 A1225A Worst-Case Commercial Conditions, VCC = 4.75 V, TJ = 70°C
I/O Module Input Propagation Delays
–2 Speed
–1 Speed
Std. Speed
Units
Parameter/Description
Min.
Max.
Min.
Max.
Min.
Max.
tINYH
Pad to Y High
2.9
3.3
3.8
ns
tINYL
Pad to Y Low
2.6
3.0
3.5
ns
tINGH
G to Y High
5.0
5.7
6.6
ns
tINGL
G to Y Low
4.7
5.4
6.3
ns
Input Module Predicted Input Routing Delays*
tIRD1
FO = 1 Routing Delay
4.1
4.6
5.4
ns
tIRD2
FO = 2 Routing Delay
4.6
5.2
6.1
ns
tIRD3
FO = 3 Routing Delay
5.3
6.0
7.1
ns
tIRD4
FO = 4 Routing Delay
5.7
6.4
7.6
ns
tIRD8
FO = 8 Routing Delay
7.4
8.3
9.8
ns
Global Clock Network
tCKH
Input Low to High
FO = 32
10.2
11.0
12.8
ns
FO = 256
11.8
13.0
15.7
tCKL
Input High to Low
FO = 32
10.2
11.0
12.8
ns
FO = 256
12.0
13.2
15.9
tPWH
Minimum Pulse Width High
FO = 32
3.4
4.1
4.5
ns
FO = 256
3.8
4.5
5.0
tPWL
Minimum Pulse Width Low
FO = 32
3.4
4.1
4.5
ns
FO = 256
3.8
4.5
5.0
tCKSW
Maximum Skew
FO = 32
0.7
ns
FO = 256
3.5
tSUEXT
Input Latch External Setup
FO = 32
0.0
ns
FO = 256
0.0
tHEXT
Input Latch External Hold
FO = 32
7.0
ns
FO = 256
11.2
tP
Minimum Period
FO = 32
7.7
8.3
9.1
ns
FO = 256
8.1
8.8
10.0
fMAX
Maximum Frequency
FO = 32
130.0
120.0
110.0
ns
FO = 256
125.0
115.0
100.0
Note:
*These parameters should be used for estimating device performance. Optimization techniques may further
reduce delays by 0 to 4 ns. Routing delays are for typical designs across worst-case operating conditions. Post-
route timing analysis or simulation is required to determine actual worst-case performance. Post-route timing is
based on actual routing delay measurements performed on the device prior to shipment.
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