ACT 2 Timing Model1 Notes: 1. Values shown for A1240A-2 at worst-" />
參數(shù)資料
型號: A1240A-TQG176C
廠商: Microsemi SoC
文件頁數(shù): 5/54頁
文件大小: 0K
描述: IC FPGA 4K GATES 176-TQFP COM
標準包裝: 40
系列: ACT™ 2
LAB/CLB數(shù): 684
輸入/輸出數(shù): 104
門數(shù): 4000
電源電壓: 4.5 V ~ 5.5 V
安裝類型: 表面貼裝
工作溫度: 0°C ~ 70°C
封裝/外殼: 176-LQFP
供應(yīng)商設(shè)備封裝: 176-TQFP(24x24)
ACT 2 Family FPGAs
R e visio n 8
2 -7
ACT 2 Timing Model1
Notes:
1. Values shown for A1240A-2 at worst-case commercial conditions.
2. Input module predicted routing delay
Figure 2-1
Timing Model
Output Delays
Internal Delays
Input Delays
tINH = 2.0 ns
tINSU= 4.0 ns
I/O Module
D
Q
tINGL= 4.7 ns
tINYL= 2.6 ns tIRD2= 4.8 ns(2)
Combinatorial
Logic Module
tPD= 3.8 ns
Sequential
Logic Module
I/O Module
tRD1 = 1.4 ns
tDLH = 8.0 ns
I/O Module
ARRAY
CLOCKS
FMAX= 100 MHz
Combin-
atorial
Logic
Included
in t
SUD
D
Q
D
Q
tOUTH = 0.0 ns
tOUTSU= 0.4 ns
tGLH = 9.0 ns
tDLH = 8.0 ns
tENHZ = 7.1 ns
tRD1= 1.4 ns
tCO= 3.8 ns
tSUD= 0.4 ns
tHD= 0.0 ns
tRD4 = 3.1 ns
tRD8 = 4.7 ns
Predicted
Routing
Delays
tCKH= 11.8 ns
G
FO = 256
tRD2 = 1.7 ns
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