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參數(shù)資料
| 型號： | A1351LKTTN-T |
| 廠商： | Allegro Microsystems Inc |
| 文件頁數(shù)： | 17/24頁 |
| 文件大?。?/td> | 663K |
| 描述： | IC SENSOR HALL EFFECT 4-SIP |
| 產(chǎn)品培訓(xùn)模塊： | Current Sensor |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 傳感范圍： | 0.055% ~ 0.095% DC/G |
| 類型： | 線性 - 單極，雙極 |
| 電源電壓： | 4.5 V ~ 5.5 V |
| 電流 - 電源： | 10mA |
| 電流 - 輸出（最大）： | 1mA |
| 輸出類型： | 數(shù)字，推挽式 |
| 特點(diǎn)： | 高精度 |
| 工作溫度： | -40°C ~ 125°C |
| 封裝/外殼： | 4-SIP |
| 供應(yīng)商設(shè)備封裝： | 4-SIP |
| 包裝： | 標(biāo)準(zhǔn)包裝 |
| 產(chǎn)品目錄頁面： | 1139 (CN2011-ZH PDF) |
| 其它名稱： | 620-1228-6 |
A1351
High Precision Linear Hall Effect Sensor IC
with a Push/Pull, Pulse Width Modulated Output
16
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Parameter Selection
Each of the five programmable parameters can be accessed
through its corresponding parameter register. There is also a
LOCK register. These registers and their parameters are:
Register 1:
" Sensitivity, Sens
" Coarse quiescent duty cycle, D
(Q)
Register 2:
" Quiescent duty cycle output, D
(Q)
Register 3:
" PWM carrier frequency, f
PWM
" Calibration test mode
Register 5:
" Overall device locking, LOCK
To select a register, a sequence of one V
PH
pulse, the key for the
register, and a second V
PH
pulse (with no VCC supply interrup-
tions) must be applied serially to the PWMOUT pin. The pulse
train used for selection of the first register, key 1, is shown in
figure 1.
V+
0
t
LOW
t
ACTIVE
V
P(HIGH)
V
P(MID)
V
P(LOW)
Figure 1. Parameter selection pulse train. This shows the sequence for
selecting the register corresponding to key 1, indicated by a single V
PM
pulse.
After the falling edge of the second V
PH
pulse, the selected regis-
ter bit field may be addressed with the appropriate code (see Bit
Field Addressing section, below).
Bit Field Addressing
After the register of a programmable parameter has been selected
as described above, the code pulses must be applied serially to
the PWMOUT pin with no VCC supply interruptions. As each
additional pulse in the code is transmitted, the overall setting of
the bit field increments by 1, up to the maximum possible code
for that register (see the Programming Logic table). The A1351
logic interprets the overall setting (the binary sum of all of the
activated or blown fuses) and applies it to the value of the param-
eter, according to the step size for the parameter (shown in the
Electrical Characteristics table).
Addressing activates the corresponding fuse locations in the
given bit field by incrementing the binary value of an internal
DAC. Measurements can be taken after each pulse to determine
if the desired result for the programmable parameter has been
reached. Cycling the supply voltage resets all the locations in the
bit field that have unblown fuses to their initial states.
t
LOW
t
ACTIVE
V
P(MID)
V
P(LOW)
V+
0
Figure 2. Bit eld addressing pulse train. Addressing the bit eld by incre-
menting the code causes the programmable parameter value to change.
The number of bits available for a given programming code, n, varies
among parameters; for example, the bit eld for Sensitivity has 8 bits avail-
able, which allows 255 separate codes to be used.
Fuse Blowing
After the required code is found for a given parameter, its value
can be set permanently by blowing individual fuses in the appro-
priate register bit field. Blowing is accomplished by applying a
high voltage pulse, called a blow pulse, of sufficient duration to
permanently set an addressed bit by blowing a fuse internal to the
device. Due to power requirements, the fuse for each bit in the
bit field must be blown individually. To accomplish this, the code
representing the desired parameter value must be translated to a
binary number. For example, as shown in figure 3, decimal code
5 is equivalent to the binary number 101. Therefore bit 2 (code
4) must be addressed and blown, the device power supply cycled,
and then bit 0 (code 1) addressed and blown. The order of blow-
ing bits, however, is not important. Blowing bit 0 first, and then
bit 2, is acceptable.
Programming Procedures
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