A1351
High Precision Linear Hall Effect Sensor IC
with a Push/Pull, Pulse Width Modulated Output
4
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
OPERATING CHARACTERISTICS (continued) valid over full operating temperature range, T
A
; C
BYPASS
= 0.1 糉, V
CC
= 5 V, unless otherwise speci ed
Continued on the next page&
Characteristic
Symbol
Test Conditions
Min.   Typ.  Max.  Units
Quiescent Duty Cycle Programming
Initial Quiescent Duty Cycle Output
D
(Q)UNIinit
B = 0 G, T
A
= 25癈
    19.5       % D
D
(Q)BIinit
B = 0 G, T
A
= 25癈
   D
(Q)PRE
   % D
Coarse Quiescent Duty Cycle Output
Programming Bits
6
1
    bit
Guaranteed Quiescent Duty Cycle Output
Range
7
D
(Q)UNI
B = 0 G, T
A
= 25癈
10        25   % D
D
(Q)BI
B = 0 G, T
A
= 25癈
36        66   % D
Quiescent Duty Cycle Output Programming
Bits
9
    bit
Average Quiescent Duty Cycle Output Step
Size
8, 9
Step
D(Q)
T
A
= 25癈
0.07   0.08   0.09   % D
Quiescent Duty Cycle Output Programming
Resolution
10
Err
PGD(Q)
T
A
= 25癈
Step
D(Q)
??. 5
   % D
Sensitivity Programming
Initial Sensitivity
Sens
init
   Sens
PRE
   % D/G
Guaranteed Sensitivity Range
11
Sens   T
A
= 25癈
0.055      0.095  % D/G
Sensitivity Programming Bits
8
    bit
Average Sensitivity Step Size
8, 9
Step
SENS
T
A
= 25癈
700   785   870  ? D/G
Sensitivity Programming Resolution
10
Err
PGSENS
T
A
= 25癈
Step
SENS
? ?.5
   ? D/G
Carrier Frequency Programming
Guaranteed Carrier Frequency Programming
Range
1,13
f
PWM
105   125   160   Hz
Carrier Frequency Programming Bits
4
    bit
Average Carrier Frequency Step Size
8, 9
Step
fPWM
T
A
= 25癈
5    6.7    8    Hz
Carrier Frequency Programming Resolution
10
Err
PGfPWM
Step
fPWM
??.5
Hz
Calibration Test Mode Programming
Calibration Test Mode Selection Bit
CAL
1
    bit
Lock Bit Programming
Overall Programming Lock Bit
LOCK
1
    bit
Factory Programmed Temperature Coefficients
Sensitivity Temperature Coefficient
12
TC
Sens
T
A
= 125 癈
0
   %/癈
Sensitivity Temperature Coefficient Error
Err
TCSENS
T
A
= 125 癈
   < ?.01      %/癈
Quiescent Duty Cycle Drift
12
D
(Q)
T
A
= 125 癈
0
   % D
Quiescent Duty Cycle Drift Error
ErrD
(Q)
T
A
= 125 癈, Sens = Sens
PRE
   < ?.2      % D