- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄4179 > A1425A-1CQ132C (Microsemi SoC)IC FPGA 2500 GATES 132-CQFP PDF資料下載
參數(shù)資料
| 型號： | A1425A-1CQ132C |
| 廠商： | Microsemi SoC |
| 文件頁數(shù)： | 8/90頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC FPGA 2500 GATES 132-CQFP |
| 產(chǎn)品變化通告： | A1425A Family Discontinuation 23/Jan/2012 |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | ACT™ 3 |
| LAB/CLB數(shù)： | 310 |
| 輸入/輸出數(shù)： | 100 |
| 門數(shù)： | 2500 |
| 電源電壓： | 4.5 V ~ 5.5 V |
| 安裝類型： | 表面貼裝 |
| 工作溫度： | 0°C ~ 70°C |
| 封裝/外殼： | 132-BCQFP，帶拉桿 |
| 供應(yīng)商設(shè)備封裝： | 132-CQFP（63.5x63.5） |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁當(dāng)前第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁
Detailed Specifications
2- 8
R e v ision 3
Module Output Connections
Module outputs have dedicated output segments. Output segments extend vertically two channels above
and two channels below, except at the top or bottom of the array. Output segments twist, as shown in
Figure 10, so that only four vertical tracks are required.
LVT Connections
Outputs may also connect to nondedicated segments called Long Vertical Tracks (LVTs). Each module
pair in the array shares four LVTs that span the length of the column. Any module in the column pair can
connect to one of the LVTs in the column using an FF connection. The FF connection uses antifuses
connected directly to the driver stage of the module output, bypassing the isolation transistor. FF
antifuses are programmed at a higher current level than HF, VF, or XF antifuses to produce a lower
resistance value.
Antifuse Connections
In general every intersection of a vertical segment and a horizontal segment contains an unprogrammed
antifuse (XF-type). One exception is in the case of the clock networks.
Clock Connections
To minimize loading on the clock networks, a subset of inputs has antifuses on the clock tracks. Only a
few of the C-module and S-module inputs can be connected to the clock networks. To further reduce
loading on the clock network, only a subset of the horizontal routing tracks can connect to the clock
inputs of the S-module.
Programming and Test Circuits
The array of logic and I/O modules is surrounded by test and programming circuits controlled by the
temporary special I/O pins MODE, SDI, and DCLK. The function of these pins is similar to all ACT family
devices. The ACT 3 family also includes support for two Actionprobe circuits, allowing complete
observability of any logic or I/O module in the array using the temporary special I/O pins, PRA and PRB.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ASC49DRYH-S734 | CONN EDGECARD 98POS DIP .100 SLD |
| ACC65DRES-S734 | CONN EDGECARD 130PS .100 EYELET |
| ABB106DHNT-S621 | CONN EDGECARD 212PS .050 DIP SLD |
| ACB106DHHT-S621 | CONN EDGECARD 212PS .050 DIP SLD |
| ABB106DHHT-S621 | CONN EDGECARD 212PS .050 DIP SLD |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| A1425A-1CQ132M | 制造商:Microsemi Corporation 功能描述:IC FPGA 100 I/O 132CQFP |
| A1425A-1CQ256B | 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:HiRel FPGAs |
| A1425A-1CQ256C | 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:HiRel FPGAs |
| A1425A-1CQ256E | 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:HiRel FPGAs |
| A1425A-1CQ256M | 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:HiRel FPGAs |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。