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參數(shù)資料
| 型號： | A1425A-2VQG100C |
| 元件分類： | FPGA |
| 英文描述： | FPGA, 310 CLBS, 2500 GATES, 200 MHz, PQFP100 |
| 封裝： | 1 MM HEIGHT, VQFP-100 |
| 文件頁數(shù)： | 16/68頁 |
| 文件大?。?/td> | 489K |
| 代理商： | A1425A-2VQG100C |
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1-197
Accelerator Series FPGAs – ACT 3 Family
Predictable Performance:
Tightest Delay Distributions
Propagation delay between logic modules depends on the
resistive and capacitive loading of the routing tracks, the
interconnect elements, and the module inputs being driven.
Propagation delay increases as the length of routing tracks,
the number of interconnect elements, or the number of
inputs increases.
From a design perspective, the propagation delay can be
statistically correlated or modeled by the fanout (number of
loads) driven by a module. Higher fanout usually requires
some paths to have longer lengths of routing track.
The ACT 3 family delivers the tightest fanout delay
distribution of any FPGA. This tight distribution is achieved
in two ways: by decreasing the delay of the interconnect
elements and by decreasing the number of interconnect
elements per path.
Actel’s patented PLICE antifuse offers a very low
resistive/capacitive interconnect. The ACT 3 family’s
antifuses, fabricated in 0.8 micron m lithography, offer
nominal levels of 200
resistance and 6 femtofarad (fF)
capacitance per antifuse.
The ACT 3 fanout distribution is also tighter than alternative
devices due to the low number of antifuses required per
interconnect
path.
The
ACT
3
family’s
proprietary
architecture limits the number of antifuses per path to only
four, with 90% of interconnects using only two antifuses.
The ACT 3 family’s tight fanout delay distribution offers an
FPGA design environment in which fanout can be traded for
the increased performance of reduced logic level designs.
This also simplifies performance estimates when designing
with ACT 3 devices.
Timing Characteristics
Timing characteristics for ACT 3 devices fall into three
categories: family dependent, device dependent, and design
dependent. The input and output buffer characteristics are
common to all ACT 3 family members. Internal routing delays
are device dependent. Design dependency means actual
delays are not determined until after placement and routing
of the user’s design is complete. Delay values may then be
determined by using the ALS Timer utility or performing
simulation with post-layout delays.
Critical Nets and Typical Nets
Propagation delays are expressed only for typical nets, which
are used for initial design performance evaluation. Critical
net delays can then be applied to the most time-critical
paths. Critical nets are determined by net property
assignment prior to placement and routing. Up to 6% of the
nets in a design may be designated as critical, while 90% of
the nets in a design are typical.
Long Tracks
Some nets in the design use long tracks. Long tracks are
special routing resources that span multiple rows, columns,
or modules.
Long tracks employ three and sometimes four
antifuse connections. This increases capacitance and
resistance, resulting in longer net delays for macros
connected to long tracks. Typically up to 6% of nets in a fully
utilized device require long tracks. Long tracks contribute
approximatley 4 ns to 14 ns delay. This additional delay is
represented statistically in higher fanout (FO=8) routing
delays in the data sheet specifications section.
Timing Derating
ACT 3 devices are manufactured in a CMOS process.
Therefore,
device
performance
varies
according
to
temperature, voltage, and process variations. Minimum
timing parameters reflect maximum operating voltage,
minimum operating temperature, and best-case processing.
Maximum timing parameters reflect minimum operating
voltage, maximum operating temperature, and worst-case
processing.
Table 2 Logic Module and Routing Delay by Fanout (ns)
(Worst-Case Commercial Conditions)
Speed
FO=1
FO=2
FO=3
FO=4
FO=8
ACT 3 –3
2.9
3.2
3.4
3.7
4.8
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| A1425A-2VQG100I | FPGA, 310 CLBS, 2500 GATES, PQFP100 |
| A1425A-PLG84C | FPGA, 310 CLBS, 2500 GATES, 125 MHz, PQCC84 |
| A1425A-PLG84I | FPGA, 310 CLBS, 2500 GATES, PQCC84 |
| A1425A-PQG100C | FPGA, 310 CLBS, 2500 GATES, 125 MHz, PQFP100 |
| A1425A-PQG100I | FPGA, 310 CLBS, 2500 GATES, PQFP100 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| A1425A-2VQG100I | 制造商:Microsemi Corporation 功能描述:FPGA ACT 3 2.5K GATES 310 CELLS 200MHZ 0.8UM 5V 100VQFP - Trays |
| A1425A-3PL84C | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field Programmable Gate Array (FPGA) |
| A1425A-3PL84I | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field Programmable Gate Array (FPGA) |
| A1425A-3PQ100C | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field Programmable Gate Array (FPGA) |
| A1425A-3PQ100I | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field Programmable Gate Array (FPGA) |
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