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參數(shù)資料
| 型號： | A1425A-2VQG100C |
| 元件分類： | FPGA |
| 英文描述： | FPGA, 310 CLBS, 2500 GATES, 200 MHz, PQFP100 |
| 封裝： | 1 MM HEIGHT, VQFP-100 |
| 文件頁數(shù)： | 8/68頁 |
| 文件大?。?/td> | 489K |
| 代理商： | A1425A-2VQG100C |
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1-190
Package Thermal Characteristics
The device junction to case thermal characteristic is
θjc, and
the junction to ambient air characteristic is
θja. The thermal
characteristics for
θja are shown with two different air flow
rates.
Maximum junction temperature is 150
°C.
A sample calculation of the absolute maximum power
dissipation allowed for a CPGA 175-pin package at
commercial temperature and still air is as follows:
Power Dissipation
P = [ICC standby+ Iactive] * VCC + IOL * VOL * N + IOH *
(VCC – VOH) * M
(1)
Where:
ICC standby is the current flowing when no inputs or
outputs are changing.
Iactive is the current flowing due to CMOS switching.
IOL, IOH are TTL sink/source currents.
VOL, VOH are TTL level output voltages.
N equals the number of outputs driving TTL loads to
VOL.
M equals the number of outputs driving TTL loads to
VOH.
An accurate determination of N and M is problematical
because their values depend on the design and on the system
I/O. The power can be divided into two components: static
and active.
Static Power Component
Actel FPGAs have small static power components that result
in lower power dissipation than PALs or PLDs. By integrating
multiple PALs/PLDs into one FPGA, an even greater
reduction in board-level power dissipation can be achieved.
The power due to standby current is typically a small
component of the overall power. Standby power is calculated
below for commercial, worst case conditions.
The static power dissipated by TTL loads depends on the
number of outputs driving high or low and the DC load
current. Again, this value is typically small. For instance, a
32-bit bus sinking 4 mA at 0.33 V will generate 42 mW with all
outputs driving low, and 140 mW with all outputs driving high.
The actual dissipation will average somewhere between as
I/Os switch states with time.
Package Type1
Pin Count
θjc
θja
Still Air
θja
300 ft/min
Units
Ceramic Pin Grid Array
100
133
175
207
257
20
35
30
25
22
15
17
15
14
13
8
°C/W
Ceramic Quad Flatpack
132
196
256
13
55
36
30
24
18
°C/W
Plastic Quad Flatpack
100
160
208
13
10
51
33
40
26
°C/W
Very Thin Quad Flatpack
100
12
43
35
°C/W
Thin Quad Flatpack
176
11
32
25
°C/W
Power Quad Flatpack
208
0.4
17
13
°C/W
Plastic Leaded Chip Carrier
84
12
37
28
°C/W
Plastic Ball Grid Array
225
313
10
25
23
19
17
°C/W
Note:
1.
Maximum Power Dissipation in Still Air for 160-pin PQFP package is 2.4 Watts, 208-pin PQFP package is 2.4 Watts, 100-pin PQFP package
is 1.6 Watts, 100-pin VQFP package is 1.9 Watts, 176-pin TQFP package is 2.5 Watts, 84-pin PLCC package is 2.2 Watts, 208-pin RQFP
package is 4.7 Watts, 225-pin BGA package is 3.2 Watts, 313-pin BGA package is 3.5 Watts.
Absolute Maximum Power Allowed
Max. junction temp. (
°C) – Max. ambient temp. (°C)
θja (°C/W)
------------------------------------------------------------------------------------------------------------------------------
150
°C – 70°C
25
°C/W
---------------------------------
3.2 W
=
ICC
VCC
Power
2mA
5.25 V
10.5 mW
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| A1425A-2VQG100I | FPGA, 310 CLBS, 2500 GATES, PQFP100 |
| A1425A-PLG84C | FPGA, 310 CLBS, 2500 GATES, 125 MHz, PQCC84 |
| A1425A-PLG84I | FPGA, 310 CLBS, 2500 GATES, PQCC84 |
| A1425A-PQG100C | FPGA, 310 CLBS, 2500 GATES, 125 MHz, PQFP100 |
| A1425A-PQG100I | FPGA, 310 CLBS, 2500 GATES, PQFP100 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| A1425A-2VQG100I | 制造商:Microsemi Corporation 功能描述:FPGA ACT 3 2.5K GATES 310 CELLS 200MHZ 0.8UM 5V 100VQFP - Trays |
| A1425A-3PL84C | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field Programmable Gate Array (FPGA) |
| A1425A-3PL84I | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field Programmable Gate Array (FPGA) |
| A1425A-3PQ100C | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field Programmable Gate Array (FPGA) |
| A1425A-3PQ100I | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field Programmable Gate Array (FPGA) |
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