參數(shù)資料
型號(hào): A1425A-VQG100I
元件分類: FPGA
英文描述: FPGA, 310 CLBS, 2500 GATES, PQFP100
封裝: 1 MM HEIGHT, VQFP-100
文件頁(yè)數(shù): 10/68頁(yè)
文件大?。?/td> 489K
代理商: A1425A-VQG100I
1-192
Fixed Capacitance Values for Actel FPGAs
(pF)
Fixed Clock Loads (s1/s2)
Determining Average Switching Frequency
To determine the switching frequency for a design, you must
have a detailed understanding of the data input values to the
circuit. The following guidelines are meant to represent
worst-case scenarios so that they can be generally used to
predict the upper limits of power dissipation. These
guidelines are as follows:
r1
r2
Device Type
routed_Clk1
routed_Clk2
A1415A
60
A14V15A
57
A1425A
75
A14V25A
72
A1440A
105
A14V40A
100
A1440B
105
A1460A
165
A14V60A
157
A1460B
165
A14100A
195
A14V100A
185
A14100B
195
s1
s2
Clock Loads on
Device Type
dedicated array
clock
dedicated I/O
clock
A1415A
104
80
A14V15A
104
80
A1425A
160
100
A14V25A
160
100
A1440A
288
140
A14V40A
288
140
A1440B
288
140
A1460A
432
168
A14V60A
432
168
A1460B
432
168
A14100A
697
228
A14V100A
697
228
A14100B
697
228
Logic Modules (m)
= 80% of modules
Inputs switching (n)
= # inputs/4
Outputs switching (p)
= # output/4
First routed array clock loads (q1)
= 40% of
sequential
modules
Second routed array clock loads (q2)
= 40% of
sequential
modules
Load capacitance (CL)
= 35 pF
Average logic module switching rate
(fm)
= F/10
Average input switching rate (fn)
= F/5
Average output switching rate (fp)
= F/10
Average first routed array clock rate
(fq1)
= F/2
Average second routed array clock rate
(fq2)
= F/2
Average dedicated array clock rate
(fs1)
= F
Average dedicated I/O clock rate (fs2) = F
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