參數(shù)資料
型號(hào)： A1425A-VQG100I
元件分類(lèi)： FPGA
英文描述： FPGA, 310 CLBS, 2500 GATES, PQFP100
封裝： 1 MM HEIGHT, VQFP-100
文件頁(yè)數(shù)： 68/68頁(yè)
文件大小： 489K
代理商： A1425A-VQG100I
1-183
Accelerator Series FPGAs – ACT 3 Family
I/O Pad Drivers
All pad drivers are capable of being tristate. Each buffer
connects to an associated I/O module with four signals: OE
(Output Enable), IE (Input Enable), DataOut, and DataIn.
Certain special signals used only during programming and
test also connect to the pad drivers: OUTEN (global output
enable), INEN (global input enable), and SLEW (individual
slew selection). See Figure 5.
Special I/Os
The special I/Os are of two types: temporary and permanent.
Temporary special I/Os are used during programming and
testing. They function as normal I/Os when the MODE pin is
inactive. Permanent special I/Os are user programmed as
either normal I/Os or special I/Os. Their function does not
change once the device has been programmed. The
permanent special I/Os consist of the array clock input
buffers (CLKA and CLKB), the hard-wired array clock input
buffer (HCLK), the hard-wired I/O clock input buffer
(IOCLK), and the hard-wired I/O register preset/clear input
buffer (IOPCL). Their function is determined by the I/O
macros selected.
Clock Networks
The ACT 3 architecture contains four clock networks: two
high-performance dedicated clock networks and two general
purpose routed networks. The high-performance networks
function up to 200 MHz, while the general purpose routed
networks function up to 150 MHz.
Dedicated Clocks
Dedicated clock networks support high performance by
providing
sub-nanosecond
skew
and
guaranteed
performance.
Dedicated
clock
networks
contain
no
programming elements in the path from the I/O Pad Driver to
the input of S-modules or I/O modules. There are two
dedicated clock networks: one for the array registers (HCLK),
and one for the I/O registers (IOCLK). The clock networks
are accessed by special I/Os.
Figure 4 Functional Diagram for I/O Module
D
DATAOUT
D
Q
CLR/PRE
DATAIN
IOCLK
IOPCL
Y
D
Q
CLR/PRE
ODE
MUX
1
0
MUX
1
0
MUX
0
1
MUX
3
0
1
2
S1
S0
相關(guān)PDF資料
PDF描述
A1A3-0503-01 FEMALE-MALE, RF STRAIGHT ADAPTER
A1A4-0503-01 FEMALE-MALE, RF STRAIGHT ADAPTER
A1A5-0503-01 FEMALE-MALE, RF STRAIGHT ADAPTER
A3A3-0539-01 MALE-MALE, RF STRAIGHT ADAPTER
A3A6-0539-01 MALE-MALE, RF STRAIGHT ADAPTER
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
A1425LK 功能描述:IC SENSOR HALL EFFECT AC 4-SIP RoHS:否 類(lèi)別:傳感器，轉(zhuǎn)換器 >> 磁性 - 霍爾效應(yīng)，數(shù)字式開(kāi)關(guān)，線性，羅盤(pán) (IC) 系列:- 標(biāo)準(zhǔn)包裝:1 系列:- 傳感范圍:20mT ~ 80mT 類(lèi)型:旋轉(zhuǎn) 電源電壓:4.5 V ~ 5.5 V 電流 - 電源:15mA 電流 - 輸出（最大）:- 輸出類(lèi)型:數(shù)字式，PWM，8.5 位串行 特點(diǎn):可編程 工作溫度:-40°C ~ 150°C 封裝/外殼:20-SSOP（0.209"，5.30mm 寬） 供應(yīng)商設(shè)備封裝:20-SSOP 包裝:Digi-Reel® 其它名稱(chēng):AS5132-HSST-500DKR
A1425LK-T 功能描述:IC SENSOR HALL EFFECT AC 4-SIP RoHS:是 類(lèi)別:傳感器，轉(zhuǎn)換器 >> 磁性 - 霍爾效應(yīng)，數(shù)字式開(kāi)關(guān)，線性，羅盤(pán) (IC) 系列:- 標(biāo)準(zhǔn)包裝:1 系列:- 傳感范圍:20mT ~ 80mT 類(lèi)型:旋轉(zhuǎn) 電源電壓:4.5 V ~ 5.5 V 電流 - 電源:15mA 電流 - 輸出（最大）:- 輸出類(lèi)型:數(shù)字式，PWM，8.5 位串行 特點(diǎn):可編程 工作溫度:-40°C ~ 150°C 封裝/外殼:20-SSOP（0.209"，5.30mm 寬） 供應(yīng)商設(shè)備封裝:20-SSOP 包裝:Digi-Reel® 其它名稱(chēng):AS5132-HSST-500DKR
A1425-PQ160C 制造商:Microsemi SOC Products Group 功能描述:
A1428AG1 制造商:DBLECTRO 制造商全稱(chēng):DB Lectro Inc 功能描述:DIP PLUG PITCH:2.54mm
A1428AG2 制造商:DBLECTRO 制造商全稱(chēng):DB Lectro Inc 功能描述:DIP PLUG PITCH:2.54mm
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫(xiě)一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*