參數(shù)資料
型號: A32400DX-1BG313I
元件分類: FPGA
英文描述: FPGA, 2526 CLBS, 40000 GATES, PBGA313
封裝: BGA-313
文件頁數(shù): 22/22頁
文件大?。?/td> 217K
代理商: A32400DX-1BG313I
9
3200DX Field Programmable Gate Arrays – The System Logic Integrator Family
the JTAG testing of the device. The JTAG test mode is
determined by the bit stream entered on the TMS pin. The
table below describes the JTAG instructions supported by the
3200DX.
Actionprobe
If a device has been successfully programmed and the
security fuse has not been programmed, any internal logic or
I/O module output can be observed using the Actionprobe
circuitry and the PRA and/or PRB pins. The Actionprobe
diagnostic system provides the software and hardware
required to perform real-time debugging. Refer to Actel’s
1995 Data Book for further information on using the
Actionprobe facility.
Test Mode
Code
Description
EXTEST
000
Allows the external circuitry
and board-level
interconnections to be tested
by forcing a test pattern at the
output pins and capturing test
results at the input pins.
SAMPLE/
PRELOAD
001
Allows a snapshot of the
signals at the device pins to be
captured and examined during
device operation.
INTEST
010
Refer to IEEE 1149.1
Specication
JPROBE
011
A private instruction allowing
the user to connect Actel’s
Micro Probe registers to the
JTAG chain.
USER
INSTRUCTION
100
Allows the user to build
application-specic
instructions such as RAM
READ and RAM WRITE.
HIGH Z
101
Refer to IEEE 1149.1
Specication
CLAMP
110
Refer to IEEE 1149.1
Specication
BYPASS
111
Enables the by bypass register
between the TDI and TDO
pins. The test data passes
through the selected device to
adjacent devices in the JTAG
chain.
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A32400DX-1PQ240C FPGA, 2526 CLBS, 40000 GATES, PQFP240
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