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SRAM and FIFO Memories in Actel’s Low-Power Flash Devices
6 – SRAM and FIFO Memories in Actel's Low-
Power Flash Devices
Introduction
As design complexity grows, greater demands are placed upon an FPGA's embedded memory. Actel
IGLOO, Fusion, and ProASIC3 devices provide the flexibility of true dual-port and two-port SRAM
blocks. The embedded memory, along with built-in, dedicated FIFO control logic, can be used to
create cascading RAM blocks and FIFOs without using additional logic gates.
IGLOO, IGLOO PLUS, and ProASIC3L FPGAs contain an additional feature that allows the device to
be put in a low-power mode called Flash*Freeze. In this mode, the core draws minimal power (on
the order of 4 to 127 W) and still retains values on the embedded SRAM/FIFO and registers.
Flash*Freeze technology allows the user to switch to Active mode on demand, thus simplifying
power management and the use of SRAM/FIFOs.
Device Architecture
The low-power flash devices feature up to 504 kbits of RAM in 4,608-bit blocks (
Figure 6-1 onthe datasheets. These memory blocks are arranged along the top and bottom of the device to
allow better access from the core and I/O (in some devices, they are only available on the north side
of the device). Every RAM block has a flexible, hardwired, embedded FIFO controller, enabling the
user to implement efficient FIFOs without sacrificing user gates.
In the IGLOO and ProASIC3 families of devices, the following memories are supported:
15 k and 30 k gate devices do not support SRAM and FIFO.
60 k and 125 k gate devices support memories on the north side of the device only.
250 k devices and larger support memories on the north and south sides of the device.
In Fusion devices, the following memories are supported:
AFS090 and AFS250 support memories on the north side of the device only.
AFS600 and AFS1500 support memories on the north and south sides of the device.