參數(shù)資料
型號(hào): A3P1000-FGG484T
元件分類: FPGA
英文描述: FPGA, 24576 CLBS, 1000000 GATES, 350 MHz, PBGA484
封裝: 1 MM PITCH, GREEN, FBGA-484
文件頁數(shù): 5/144頁
文件大?。?/td> 4877K
代理商: A3P1000-FGG484T
Automotive ProASIC3 DC and Switching Characteristics
2- 90
R e visio n 1
Table 2-119 RAM4K9
Automotive-Case Conditions: TJ = 115°C, Worst Case VCC = 1.425 V
Parameter Description
–1
Std. Units
tAS
Address Setup Time
0.30 0.35
ns
tAH
Address Hold Time
0.00 0.00
ns
tENS
REN_B, WEN_B Setup Time
0.17 0.20
ns
tENH
REN_B, WEN_B Hold Time
0.12 0.14
ns
tBKS
BLK_B Setup Time
0.28 0.33
ns
tBKH
BLK_B Hold Time
0.02 0.03
ns
tDS
Input data (DI) Setup Time
0.22 0.26
ns
tDH
Input data (DI) Hold Time
0.00 0.00
ns
tCKQ1
Clock High to New Data Valid on DO (output retained, WMODE = 0)
2.13 2.50
ns
Clock High to New Data Valid on DO (flow-through, WMODE = 1)
2.81 3.30
ns
tCKQ2
Clock High to New Data Valid on DO (pipelined)
1.07 1.25
ns
tWRO
Address collision clk-to-clk delay for reliable read access after write on same
address
TBD TBD
ns
tCCKH
Address collision clk-to-clk delay for reliable write access after write/read on same
address
TBD TBD
ns
tRSTBQ
RESET_B Low to Data Out Low on DO (flow-through)
1.10 1.29
ns
RESET_B Low to Data Out Low on DO (pipelined)
1.10 1.29
ns
tREMRSTB
RESET_B Removal
0.34 0.40
ns
tRECRSTB
RESET_B Recovery
1.79 2.10
ns
tMPWRSTB
RESET_B Minimum Pulse Width
0.25 0.30
ns
tCYC
Clock Cycle Time
3.85 4.53
ns
FMAX
Maximum Frequency
260
221
MHz
Note:
For specific junction temperature and voltage-supply levels, refer to Table 2-5 on page 2-5 for derating values.
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