7
www.microsemi.com/soc
IGLOO
UltralowpowerFPGAs
Flash*Freezetechnologyfor
lowest power consumption
1.2VcoreandI/Ovoltage
5WFlash*Freezemode
Reprogrammable
Liveatpower-up
AES-protectedin-system
programming (ISP)
UsernonvolatileFlashROM
IGLOO/e
Notes:
1. AES is not available for Cortex-M1 IGLOO devices.
2. AGL060 in CS121 does not support the PLL.
3. Six chip (main) and twelve quadrant global networks are available for AGL060 devices and above.
4. The M1AGL250 device does not support this package.
IGLOO/e Devices
Notes:
1. The M1AGL250 device does not support QN132 or CS196 packages.
2. Each used differential pair reduces the number of single-ended I/Os available by two.
I/Os Per Package
IGLOO Devices
AGL030 AGL060 AGL125
AGL250
AGL400
AGL600
AGL1000
AGLE600
AGLE3000
Cortex-M1
Devices
M1AGL2501
M1AGL600
M1AGL1000
M1AGLE3000
I/O Type
Single-
Ended
I/O
Single-
Ended
I/O
Single-
Ended
I/O
Single-
Ended
I/O2
Differen-
tial I/O
Pairs
Single-
Ended
I/O2
Differen-
tial I/O
Pairs
Single-
Ended
I/O2
Differen-
tial I/O
Pairs
Single-
Ended
I/O2
Differen-
tial I/O
Pairs
Single-
Ended
I/O2
Differen-
tial I/O
Pairs
Single-
Ended
I/O2
Differen-
tial I/O
Pairs
QN48
34
—
QN68
49
—
UC81
66
—
CS81
66
—
CS121
—
96
—
VQ100
77
71
68
13
—
QN132
81
80
84
87
19
—
CS196
—
133
143
35
143
35
—
FG144
—
96
97
24
97
25
97
25
97
25
—
FG256
—
178
38
177
43
177
44
165
79
—
CS281
—
215
53
215
53
—
FG484
—
194
38
235
60
300
74
270
135
341
168
FG896
—
620
310
The ultra low power programmable solution
The IGLOO family of reprogrammable, full-featured flash FPGAs is designed to meet the demanding power, area and cost requirements of today’s portable
electronics. Based on nonvolatile flash technology, the 1.2 V to 1.5 V operating voltage family offers the industry’s lowest power consumption—as low as 5 W.
The IGLOO family supports up to 3,000,000 system gates with up to 504 Kbits of true dual-port SRAM, up to 6 embedded PLLs and up to 620 user I/Os.
Low power applications that require 32-bit processing can use the ARM Cortex-M1 processor without license fee or royalties in M1 IGLOO devices. Developed
specifically for implementation in FPGAs, Cortex-M1 offers an optimal balance between performance and size to minimize power consumption.
IGLOO Devices
AGL030
AGL060
AGL125
AGL250
AGL400
AGL600
AGL1000
AGLE600
AGLE3000
Cortex-M1Devices1
M1AGL250
M1AGL600
M1AGL1000
M1AGLE3000
System Gates
30,000
60,000
125,000
250,000
400,000
600,000
1,000,000
600,000
3,000,000
Typical Equivalent
Macrocells
256
512
1,024
2,048
—
VersaTiles(D-flip-flops)
768
1,536
3,072
6,144
9,216
13,824
24,576
13,824
75,264
Flash*Freeze Mode
(typical,W)
5
10
16
24
32
36
53
49
137
RAM(1,024bits)
—
18
36
54
108
144
108
504
RAMBlocks(4,608bits)
—
4
8
12
24
32
24
112
FlashROMKbits
(1,024bits)
1
AES-Protected ISP1
—
Yes
Integrated PLLs with CCC2
—
1
6
VersaNetGlobals3
6
18
I/OBanks
2
4
8
Maximum User I/Os
(packaged device)
81
96
133
143
194
235
300
270
620
Package Pins
UC
CS
QN
VQ
FG
UC81
CS81
QN48
QN68
QN132
VQ100
CS121
QN132
VQ100
FG1445
CS81
CS196
QN132
VQ100
FG144
CS81
CS1964
QN1324
VQ100
FG144
CS196
FG144
FG256
FG484
CS281
FG144
FG256
FG484
CS281
FG144
FG256
FG484
FG256
FG484
FG896