Revision 13 2-29 2.5 V LVCMOS Low-Voltage CMOS for 2.5 V is an extension of the LVCMOS standard (JESD8-5) used" />
參數(shù)資料
型號: A3PE600-1FG256
廠商: Microsemi SoC
文件頁數(shù): 101/162頁
文件大小: 0K
描述: IC FPGA 600000 GATES 256-FBGA
標準包裝: 90
系列: ProASIC3E
RAM 位總計: 110592
輸入/輸出數(shù): 165
門數(shù): 600000
電源電壓: 1.425 V ~ 1.575 V
安裝類型: 表面貼裝
工作溫度: 0°C ~ 70°C
封裝/外殼: 256-LBGA
供應商設備封裝: 256-FPBGA(17x17)
ProASIC3E Flash Family FPGAs
Revision 13
2-29
2.5 V LVCMOS
Low-Voltage CMOS for 2.5 V is an extension of the LVCMOS standard (JESD8-5) used for general-
purpose 2.5 V applications.
Table 2-33 Minimum and Maximum DC Input and Output Levels
2.5 V
LVCMOS
VIL
VIH
VOL
VOH
IOL IOH
IOSL
IOSH
IIL1 IIH2
Drive
Strength
Min.
V
Max.
V
Min.
V
Max.
V
Max.,
V
Min.
VmA mA
Max.
mA3
Max.
mA3
A4 A4
4 mA
–0.3
0.7
1.7
3.6
0.7
1.7
4
18
16
10
8 mA
–0.3
0.7
1.7
3.6
0.7
1.7
8
37
32
10
12 mA
–0.3
0.7
1.7
3.6
0.7
1.7
12 12
74
65
10
16 mA
–0.3
0.7
1.7
3.6
0.7
1.7
16 16
87
83
10
24 mA
–0.3
0.7
1.7
3.6
0.7
1.7
24 24
124
169
10
Notes:
1. IIL is the input leakage current per I/O pin over recommended operation conditions where –0.3 V < VIN < VIL.
2. IIH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input current is
larger when operating outside recommended ranges.
3. Currents are measured at high temperature (100°C junction temperature) and maximum voltage.
4. Currents are measured at 85°C junction temperature.
5. Software default selection highlighted in gray.
Figure 2-8 AC Loading
Table 2-34 AC Waveforms, Measuring Points, and Capacitive Loads
Input Low (V)
Input High (V)
Measuring Point* (V)
VREF (typ.) (V)
CLOAD (pF)
0
2.5
1.2
35
Note: *Measuring point = Vtrip. See Table 2-15 on page 2-18 for a complete table of trip points.
Test Point
Enable Path
Datapath
35 pF
R = 1 k
R to VCCI for tLZ / tZL / tZLS
R to GND for tHZ / tZH / tZHS
35 pF for tZH / tZHS / tZL / tZLS
35 pF for tHZ / tLZ
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