參數(shù)資料
型號(hào): A40MX04-FVQ80X79
元件分類: FPGA
英文描述: FPGA, 547 CLBS, 6000 GATES, 48 MHz, PQFP80
封裝: 1 MM HEIGHT, PLASTIC, VQFP-80
文件頁數(shù): 44/124頁
文件大?。?/td> 3142K
代理商: A40MX04-FVQ80X79
40MX and 42MX FPGA Families
1- 20
v6.1
Output Drive Characteristics for 3.3V PCI Signaling
Table 19
DC Specification (3.3V PCI Signaling)1
PCI
MX
Symbol
Parameter
Condition
Min.
Max.
Min.
Max.
Units
VCCI
Supply Voltage for I/Os
3.0
3.6
3.0
3.6
V
VIH
Input High Voltage
0.5
VCC + 0.5
0.5
VCCI + 0.3
V
VIL
Input Low Voltage
–0.5
0.8
–0.3
0.8
V
IIH
Input High Leakage Current
VIN = 2.7V
70
10
A
IIL
Input Leakage Current
–70
–10
A
VOH
Output High Voltage
IOUT = –2 mA
0.9
3.3
V
VOL
Output Low Voltage
IOUT = 3 mA,
6 mA
0.1
0.1 VCCI
V
CIN
Input Pin Capacitance
10
pF
CCLK
CLK Pin Capacitance
5
12
10
pF
LPIN
Pin Inductance
20
< 8 nH3
nH
Notes:
1. PCI Local Bus Specification, Version 2.1, Section 4.2.2.1.
2. Maximum rating for VCCI –0.5V to 7.0V.
3. Dependent upon the chosen package. PCI recommends QFP and BGA packaging to reduce pin inductance and capacitance.
Table 20
AC Specifications for (3.3V PCI Signaling)*
PCI
MX
Symbol
Parameter
Condition
Min.
Max.
Min.
Max.
Units
ICL
Low Clamp Current
–5 < VIN –1
–25 + (VIN +1)
/0.015
–60
–10
mA
Slew (r)
Output Rise Slew Rate
0.2V to 0.6V load
1
4
1.8
2.8
V/ns
Slew (f)
Output Fall Slew Rate
0.6V to 0.2V load
1
4
2.8
4.0
V/ns
Note: *PCI Local Bus Specification, Version 2.1, Section 4.2.2.2.
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A40MX04-FVQ80 FPGA, 547 CLBS, 6000 GATES, 48 MHz, PQFP80
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