參數(shù)資料
型號(hào)： A40MX04-FVQ80X79
元件分類： FPGA
英文描述： FPGA, 547 CLBS, 6000 GATES, 48 MHz, PQFP80
封裝： 1 MM HEIGHT, PLASTIC, VQFP-80
文件頁數(shù)： 96/124頁
文件大?。?/td> 3142K
代理商： A40MX04-FVQ80X79
40MX and 42MX FPGA Families
v6.1
1-67
Input Module Predicted Routing Delays2
tIRD1
FO=1 Routing Delay
2.6
2.9
3.2
3.8
5.3
ns
tIRD2
FO=2 Routing Delay
2.9
3.2
3.6
4.3
6.0
ns
tIRD3
FO=3 Routing Delay
3.2
3.6
4.0
4.8
6.6
ns
tIRD4
FO=4 Routing Delay
3.5
3.9
4.4
5.2
7.3
ns
tIRD8
FO=8 Routing Delay
4.8
5.3
6.1
7.1
10.0
ns
Global Clock Network
tCKH
Input LOW to HIGH
FO=32
FO=486
4.4
4.8
5.3
5.5
6.0
6.5
7.1
9.1
10.0
ns
tCKL
Input HIGH to LOW
FO=32
FO=486
5.1
6.0
5.7
6.6
6.4
7.5
7.6
8.8
10.6
12.4
ns
tPWH
Minimum Pulse
Width HIGH
FO=32
FO=486
3.0
3.3
3.7
3.8
4.2
4.5
4.9
6.3
6.9
ns
tPWL
Minimum Pulse
Width LOW
FO=32
FO=486
3.0
3.3
3.4
3.7
3.8
4.2
4.5
4.9
6.3
6.9
ns
tCKSW
Maximum Skew
FO=32
FO=486
0.8
1.0
1.1
1.6
ns
tSUEXT
Input Latch External
Set-Up
FO=32
FO=486
0.0
ns
TTL Output Module Timing5
tDLH
Data-to-Pad HIGH
3.4
3.8
4.3
5.0
7.1
ns
tDHL
Data-to-Pad LOW
4.0
4.4
5.0
5.9
8.3
ns
tENZH
Enable Pad Z to HIGH
3.6
4.0
4.5
5.3
7.4
ns
tENZL
Enable Pad Z to LOW
3.9
4.4
5.0
5.8
8.2
ns
tENHZ
Enable Pad HIGH to Z
7.2
8.0
9.1
10.7
14.9
ns
tENLZ
Enable Pad LOW to Z
6.7
7.5
8.5
9.9
13.9
ns
tGLH
G-to-Pad HIGH
4.8
5.3
6.0
7.2
10.0
ns
tGHL
G-to-Pad LOW
4.8
5.3
6.0
7.2
10.0
ns
tLSU
I/O Latch Output Set-Up
0.7
0.8
1.0
1.4
ns
Table 37
A42MX24 Timing Characteristics (Nominal 3.3V Operation) (Continued)
(Worst-Case Commercial Conditions, VCCA = 3.0V, TJ = 70°C)
‘–3’ Speed
‘–2’Speed
‘–1’ Speed
‘Std’ Speed
‘–F’ Speed
Units
Parameter Description
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Notes:
1. For dual-module macros, use tPD1 + tRD1 + tPDn, tCO + tRD1 + tPDn, or tPD1 + tRD1 + tSUD, whichever is appropriate.
2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating
device performance. Post-route timing analysis or simulation is required to determine actual performance.
3. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules can be
obtained from the Timer utility.
4. Set-up and hold timing parameters for the Input Buffer Latch are defined with respect to the PAD and the D input. External setup/
hold timing parameters must account for delay from an external PAD signal to the G inputs. Delay from an external PAD signal to
the G input subtracts (adds) to the internal setup (hold) time.
5. Delays based on 35 pF loading.
相關(guān)PDF資料
PDF描述
A40MX04-FVQ80 FPGA, 547 CLBS, 6000 GATES, 48 MHz, PQFP80
A40MX04-PL44IX79 FPGA, 547 CLBS, 6000 GATES, 80 MHz, PQCC44
A40MX04-PL44I FPGA, 547 CLBS, 6000 GATES, 80 MHz, PQCC44
A40MX04-PL44MX79 FPGA, 547 CLBS, 6000 GATES, 80 MHz, PQCC44
A40MX04-PL44M FPGA, 547 CLBS, 6000 GATES, 80 MHz, PQCC44
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
A40MX04-FVQG80 功能描述:IC FPGA MX SGL CHIP 6K 80-VQFP RoHS:是 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場(chǎng)可編程門陣列） 系列:MX 標(biāo)準(zhǔn)包裝:152 系列:IGLOO PLUS LAB/CLB數(shù):- 邏輯元件/單元數(shù):792 RAM 位總計(jì):- 輸入/輸出數(shù):120 門數(shù):30000 電源電壓:1.14 V ~ 1.575 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 85°C 封裝/外殼:289-TFBGA，CSBGA 供應(yīng)商設(shè)備封裝:289-CSP（14x14）
A40MX04-PL100 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:40MX and 42MX FPGA Families
A40MX04-PL100ES 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:40MX and 42MX FPGA Families
A40MX04-PL100I 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:40MX and 42MX FPGA Families
A40MX04-PL100M 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:40MX and 42MX FPGA Families
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