參數(shù)資料
型號： A42MX02-1PL100ES
廠商： Electronic Theatre Controls, Inc.
英文描述： 40MX and 42MX FPGA Families
中文描述： 40MX和42MX FPGA系列
文件頁數(shù)： 75/123頁
文件大小： 854K
代理商： A42MX02-1PL100ES
40MX and 42MX FPGA Families
v6.0
1-69
Table 38
A42MX36 Timing Characteristics (Nominal 5.0V Operation)
(Worst-Case Commercial Conditions, V
CCA
= 4.75V, T
J
= 70°C)
‘–3’ Speed
‘–2’ Speed
‘–1’ Speed
‘Std’ Speed
‘–F’ Speed
Parameter Description
Logic Module Combinatorial Functions
1
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max. Units
t
PD
t
PDD
Logic Module Predicted Routing Delays
2
Internal Array Module Delay
1.3
1.5
1.7
2.0
2.7
ns
Internal Decode Module Delay
1.6
1.8
2.0
2.4
3.3
ns
t
RD1
t
RD2
t
RD3
t
RD4
t
RD5
t
RDD
Logic Module Sequential Timing
3, 4
FO=1 Routing Delay
0.9
1.0
1.2
1.4
2.0
ns
FO=2 Routing Delay
1.3
1.4
1.6
1.9
2.7
ns
FO=3 Routing Delay
1.6
1.8
2.0
2.4
3.4
ns
FO=4 Routing Delay
2.0
2.2
2.5
2.9
4.1
ns
FO=8 Routing Delay
3.3
3.7
4.2
4.9
6.9
ns
Decode-to-Output Routing Delay
0.3
0.4
0.4
0.5
0.7
ns
t
CO
t
GO
t
SUD
t
HD
t
RO
t
SUENA
t
HENA
t
WCLKA
Flip-Flop Clock-to-Output
1.3
1.4
1.6
1.9
2.7
ns
Latch Gate-to-Output
1.3
1.4
1.6
1.9
2.7
ns
Flip-Flop (Latch) Set-Up Time
0.3
0.3
0.4
0.5
0.7
ns
Flip-Flop (Latch) Hold Time
0.0
0.0
0.0
0.0
0.0
ns
Flip-Flop (Latch) Reset-to-Output
1.6
1.7
2.0
2.3
3.2
ns
Flip-Flop (Latch) Enable Set-Up
0.7
0.8
0.9
1.0
1.4
ns
Flip-Flop (Latch) Enable Hold
0.0
0.0
0.0
0.0
0.0
ns
Flip-Flop (Latch) Clock Active
Pulse Width
3.3
3.7
4.2
4.9
6.9
ns
t
WASYN
Flip-Flop (Latch) Asynchronous
Pulse Width
4.4
4.8
5.5
6.4
9.0
ns
Synchronous SRAM Operations
t
RC
t
WC
t
RCKHL
t
RCO
t
ADSU
Notes:
1. For dual-module macros, use t
PD1
+ t
RD1
+ t
PDn
, t
CO
+ t
RD1
+ t
PDn
, or t
PD1
+ t
RD1
+ t
SUD
, whichever is appropriate.
2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating
device performance. Post-route timing analysis or simulation is required to determine actual performance.
3. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules can be
obtained from the Timer utility.
4. Set-up and hold timing parameters for the Input Buffer Latch are defined with respect to the PAD and the D input. External setup/
hold timing parameters must account for delay from an external PAD signal to the G inputs. Delay from an external PAD signal to
the G input subtracts (adds) to the internal setup (hold) time.
5. Delays based on 35 pF loading.
Read Cycle Time
6.8
7.5
8.5
10.0
14.0
ns
Write Cycle Time
6.8
7.5
8.5
10.0
14.0
ns
Clock HIGH/LOW Time
3.4
3.8
4.3
5.0
7.0
ns
Data Valid After Clock HIGH/LOW
3.4
3.8
4.3
5.0
7.0
ns
Address/Data Set-Up Time
1.6
1.8
2.0
2.4
3.4
ns
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A42MX02-1PQ100B 制造商:未知廠家 制造商全稱:未知廠家 功能描述:40MX and 42MX FPGA Families
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