參數資料
型號： A42MX02-1PL100ES
廠商： Electronic Theatre Controls, Inc.
英文描述： 40MX and 42MX FPGA Families
中文描述： 40MX和42MX FPGA系列
文件頁數： 77/123頁
文件大?。?/td> 854K
代理商： A42MX02-1PL100ES
40MX and 42MX FPGA Families
v6.0
1-71
Input Module Predicted Routing Delays
2
t
IRD1
t
IRD2
t
IRD3
t
IRD4
t
IRD8
Global Clock Network
FO=1 Routing Delay
2.0
2.2
2.5
2.9
4.1
ns
FO=2 Routing Delay
2.3
2.6
2.9
3.4
4.8
ns
FO=3 Routing Delay
2.6
2.9
3.3
3.9
5.5
ns
FO=4 Routing Delay
3.0
3.3
3.8
4.4
6.2
ns
FO=8 Routing Delay
4.3
4.8
5.5
6.4
9.0
ns
t
CKH
Input LOW to HIGH
FO=32
FO=635
2.7
3.0
3.0
3.3
3.4
3.8
4.0
4.4
5.6
6.2
ns
ns
t
CKL
Input HIGH to LOW
FO=32
FO=635
3.8
4.9
4.2
5.4
4.8
6.1
5.6
7.2
7.8
10.1
ns
ns
t
PWH
Minimum Pulse
Width HIGH
FO=32
FO=635
1.8
2.0
2.0
2.2
2.2
2.5
2.6
2.9
3.6
4.1
ns
ns
t
PWL
Minimum Pulse
Width LOW
FO=32
FO=635
1.8
2.0
2.0
2.2
2.2
2.5
2.6
2.9
3.6
4.1
ns
ns
t
CKSW
Maximum Skew
FO=32
FO=635
0.8
0.8
0.8
0.8
0.9
0.9
1.0
1.0
1.4
1.4
ns
ns
t
SUEXT
Input Latch External
Set-Up
FO=32
FO=635
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
ns
ns
t
HEXT
Input Latch External
Hold
FO=32
FO=635
2.8
3.3
3.2
3.7
3.6
4.2
4.2
4.9
5.9
6.9
ns
ns
t
P
Minimum Period
(1/f
MAX
)
Maximum Datapath
Frequency
FO=32
FO=635
5.5
6.0
6.1
6.6
6.6
7.2
7.6
8.3
12.7
13.8
ns
ns
f
MAX
FO=32
FO=635
180
166
164
151
151
139
131
121
79
73
MHz
MHz
TTL Output Module Timing
5
t
DLH
t
DHL
t
ENZH
t
ENZL
t
ENHZ
Notes:
1. For dual-module macros, use t
PD1
+ t
RD1
+ t
PDn
, t
CO
+ t
RD1
+ t
PDn
, or t
PD1
+ t
RD1
+ t
SUD
, whichever is appropriate.
2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating
device performance. Post-route timing analysis or simulation is required to determine actual performance.
3. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules can be
obtained from the Timer utility.
4. Set-up and hold timing parameters for the Input Buffer Latch are defined with respect to the PAD and the D input. External setup/
hold timing parameters must account for delay from an external PAD signal to the G inputs. Delay from an external PAD signal to
the G input subtracts (adds) to the internal setup (hold) time.
5. Delays based on 35 pF loading.
Data-to-Pad HIGH
2.6
2.8
3.2
3.8
5.3
ns
Data-to-Pad LOW
3.0
3.3
3.7
4.4
6.2
ns
Enable Pad Z to HIGH
2.7
3.0
3.3
3.9
5.5
ns
Enable Pad Z to LOW
3.0
3.3
3.7
4.3
6.1
ns
Enable Pad HIGH to Z
5.3
5.8
6.6
7.8
10.9
ns
Table 38
A42MX36 Timing Characteristics (Nominal 5.0V Operation)
(Worst-Case Commercial Conditions, V
CCA
= 4.75V, T
J
= 70°C)
‘–3’ Speed
‘–2’ Speed
‘–1’ Speed
‘Std’ Speed
‘–F’ Speed
Parameter Description
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max. Units
相關PDF資料
PDF描述
A42MX02-1PL100I 40MX and 42MX FPGA Families
A42MX02-1PL100M 40MX and 42MX FPGA Families
A42MX02-1PQ100I 40MX and 42MX FPGA Families
A42MX02-1PQ100M 40MX and 42MX FPGA Families
A42MX02-1TQ100M 40MX and 42MX FPGA Families
相關代理商/技術參數
參數描述
A42MX02-1PL100I 制造商:未知廠家 制造商全稱:未知廠家 功能描述:40MX and 42MX FPGA Families
A42MX02-1PL100M 制造商:未知廠家 制造商全稱:未知廠家 功能描述:40MX and 42MX FPGA Families
A42MX02-1PQ100 制造商:未知廠家 制造商全稱:未知廠家 功能描述:40MX and 42MX FPGA Families
A42MX02-1PQ100A 制造商:未知廠家 制造商全稱:未知廠家 功能描述:40MX and 42MX FPGA Families
A42MX02-1PQ100B 制造商:未知廠家 制造商全稱:未知廠家 功能描述:40MX and 42MX FPGA Families
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