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參數(shù)資料
| 型號： | A42MX09-1VQ100 |
| 廠商： | Microsemi SoC |
| 文件頁數(shù)： | 129/142頁 |
| 文件大小： | 0K |
| 描述： | IC FPGA MX SGL CHIP 14K 100VQFP |
| 標(biāo)準(zhǔn)包裝： | 90 |
| 系列： | MX |
| 輸入/輸出數(shù)： | 83 |
| 門數(shù)： | 14000 |
| 電源電壓： | 3 V ~ 3.6 V，4.75 V ~ 5.25 V |
| 安裝類型： | 表面貼裝 |
| 工作溫度： | 0°C ~ 70°C |
| 封裝/外殼： | 100-TQFP |
| 供應(yīng)商設(shè)備封裝： | 100-VQFP（14x14） |
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40MX and 42MX FPGA Families
Re vi s i on 11
1 - 83
Pin Descriptions
CLK/A/B, I/O
Global Clock
Clock inputs for clock distribution networks. CLK is for 40MX while CLKA and CLKB are for 42MX
devices. The clock input is buffered prior to clocking the logic modules. This pin can also be used as an
I/O.
DCLK, I/O
Diagnostic Clock
Clock input for diagnostic probe and device programming. DCLK is active when the MODE pin is HIGH.
This pin functions as an I/O when the MODE pin is LOW.
GND
Ground
Input LOW supply voltage.
I/O
Input/Output
Input, output, tristate or bidirectional buffer. Input and output levels are compatible with standard TTL and
CMOS specifications. Unused I/Os pins are configured by the Designer software as shown in Table 1-40.
In all cases, it is recommended to tie all unused MX I/O pins to LOW on the board. This applies to all
dual-purpose pins when configured as I/Os as well.
LP
Low Power Mode
Controls the low power mode of all 42MX devices. The device is placed in the low power mode by
connecting the LP pin to logic HIGH. In low power mode, all I/Os are tristated, all input buffers are turned
OFF, and the core of the device is turned OFF. To exit the low power mode, the LP pin must be set LOW.
The device enters the low power mode 800 ns after the LP pin is driven to a logic HIGH. It will resume
normal operation in 200 s after the LP pin is driven to a logic LOW.
MODE
Mode
Controls the use of multifunction pins (DCLK, PRA, PRB, SDI, TDO). The MODE pin is held HIGH to
provide verification capability. The MODE pin should be terminated to GND through a 10k
Ω resistor so
that the MODE pin can be pulled HIGH when required.
NC
No Connection
This pin is not connected to circuitry within the device. These pins can be driven to any voltage or can be
left floating with no effect on the operation of the device.
PRA, I/O
PRB, I/O
Probe A/B
The Probe pin is used to output data from any user-defined design node within the device. Each
diagnostic pin can be used in conjunction with the other probe pin to allow real-time diagnostic output of
any signal path within the device. The Probe pin can be used as a user-defined I/O when verification has
been completed. The pin's probe capabilities can be permanently disabled to protect programmed design
confidentiality. The Probe pin is accessible when the MODE pin is HIGH. This pin functions as an I/O
when the MODE pin is LOW.
QCLKA/B/C/D, I/O
Quadrant Clock
Quadrant clock inputs for A42MX36 devices. When not used as a register control signal, these pins can
function as user I/Os.
Table 1-40 Configuration of Unused I/Os
Device
Configuration
A40MX02, A40MX04
Pulled LOW
A42MX09, A42MX16
Pulled LOW
A42MX24, A42MX36
Tristated
相關(guān)PDF資料 |
PDF描述 |
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| A42MX09-VQG100I | IC FPGA MX SGL CHIP 14K 100-VQFP |
| A3P1000-1PQG208 | IC FPGA 1KB FLASH 1M 208-PQFP |
| EMC13DTEF | CONN EDGECARD 26POS .100 EYELET |
| ACB70DHFR | CONN EDGECARD 140POS .050 SMD |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| A42MX09-1VQ100A | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:40MX and 42MX FPGA Families |
| A42MX09-1VQ100B | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:40MX and 42MX FPGA Families |
| A42MX09-1VQ100ES | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:40MX and 42MX FPGA Families |
| A42MX09-1VQ100I | 功能描述:IC FPGA MX SGL CHIP 14K 100VQFP RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:MX 標(biāo)準(zhǔn)包裝:40 系列:SX-A LAB/CLB數(shù):6036 邏輯元件/單元數(shù):- RAM 位總計:- 輸入/輸出數(shù):360 門數(shù):108000 電源電壓:2.25 V ~ 5.25 V 安裝類型:表面貼裝 工作溫度:0°C ~ 70°C 封裝/外殼:484-BGA 供應(yīng)商設(shè)備封裝:484-FPBGA（27X27） |
| A42MX09-1VQ100M | 制造商:Microsemi Corporation 功能描述:FPGA 14K GATES 336 CELLS 148MHZ/247MHZ 0.45UM 3.3V/5V 100VQF - Trays 制造商:Microsemi Corporation 功能描述:IC FPGA 83 I/O 100VQFP |
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