參數(shù)資料
型號： A42MX09-1VQ100
廠商： Microsemi SoC
文件頁數(shù)： 54/142頁
文件大?。?/td> 0K
描述： IC FPGA MX SGL CHIP 14K 100VQFP
標(biāo)準(zhǔn)包裝： 90
系列： MX
輸入/輸出數(shù)： 83
門數(shù)： 14000
電源電壓： 3 V ~ 3.6 V，4.75 V ~ 5.25 V
安裝類型： 表面貼裝
工作溫度： 0°C ~ 70°C
封裝/外殼： 100-TQFP
供應(yīng)商設(shè)備封裝： 100-VQFP（14x14）
40MX and 42MX FPGA Families
Re vi s i on 11
1 - 15
JTAG Mode Activation
The JTAG test logic circuit is activated in the Designer software by selecting Tools -> Device Selection.
This brings up the Device Selection dialog box as shown in Figure 1-14. The JTAG test logic circuit can
be enabled by clicking the "Reserve JTAG Pins" check box. Table 1-5 explains the pins' behavior in
either mode.
TRST Pin and TAP Controller Reset
An active reset (TRST) pin is not supported; however, MX devices contain power-on circuitry that resets
the boundary scan circuitry upon power-up. Also, the TMS pin is equipped with an internal pull-up
resistor. This allows the TAP controller to remain in or return to the Test-Logic-Reset state when there is
no input or when a logical 1 is on the TMS pin. To reset the controller, TMS must be HIGH for at least five
TCK cycles.
Boundary Scan Description Language (BSDL) File
Conforming to the IEEE Standard 1149.1 requires that the operation of the various JTAG components be
documented. The BSDL file provides the standard format to describe the JTAG components that can be
used by automatic test equipment software. The file includes the instructions that are supported,
instruction bit pattern, and the boundary-scan chain order. For an in-depth discussion on BSDL files,
please refer to Actel BSDL Files Format Description application note.
BSDL files are grouped into two categories - generic and device-specific. The generic files assign all user
I/Os as inouts. Device-specific files assign user I/Os as inputs, outputs or inouts.
Generic files for MX devices are available on the Microsemi SoC Product Group's website:
Figure 1-14 Device Selection Wizard
Table 1-5
Boundary Scan Pin Configuration and Functionality
Reserve JTAG
Checked
Unchecked
TCK
BST input; must be terminated to logical HIGH or LOW to avoid floating
User I/O
TDI, TMS
BST input; may float or be tied to HIGH
User I/O
TDO
BST output; may float or be connected to TDI of another device
User I/O
相關(guān)PDF資料
PDF描述
A42MX09-VQG100I IC FPGA MX SGL CHIP 14K 100-VQFP
A3P1000-1PQG208 IC FPGA 1KB FLASH 1M 208-PQFP
EMC13DTEF CONN EDGECARD 26POS .100 EYELET
ACB70DHFR CONN EDGECARD 140POS .050 SMD
ABB70DHFR CONN EDGECARD 140POS .050 SMD
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
A42MX09-1VQ100A 制造商:未知廠家 制造商全稱:未知廠家 功能描述:40MX and 42MX FPGA Families
A42MX09-1VQ100B 制造商:未知廠家 制造商全稱:未知廠家 功能描述:40MX and 42MX FPGA Families
A42MX09-1VQ100ES 制造商:未知廠家 制造商全稱:未知廠家 功能描述:40MX and 42MX FPGA Families
A42MX09-1VQ100I 功能描述:IC FPGA MX SGL CHIP 14K 100VQFP RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:MX 標(biāo)準(zhǔn)包裝:40 系列:SX-A LAB/CLB數(shù):6036 邏輯元件/單元數(shù):- RAM 位總計:- 輸入/輸出數(shù):360 門數(shù):108000 電源電壓:2.25 V ~ 5.25 V 安裝類型:表面貼裝 工作溫度:0°C ~ 70°C 封裝/外殼:484-BGA 供應(yīng)商設(shè)備封裝:484-FPBGA（27X27）
A42MX09-1VQ100M 制造商:Microsemi Corporation 功能描述:FPGA 14K GATES 336 CELLS 148MHZ/247MHZ 0.45UM 3.3V/5V 100VQF - Trays 制造商:Microsemi Corporation 功能描述:IC FPGA 83 I/O 100VQFP
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