參數(shù)資料
型號： A42MX16-1PL100I
廠商： Electronic Theatre Controls, Inc.
英文描述： 40MX and 42MX FPGA Families
中文描述： 40MX和42MX FPGA系列
文件頁數(shù)： 113/120頁
文件大?。?/td> 854K
代理商： A42MX16-1PL100I
92
4958B–AUTO–11/10
Atmel ATA6285/ATA6286 [Preliminary]
Bit 1 - T2CIM: Timer2 Compare Interrupt Mask Bit
Writing this bit to one enables an interrupt on the T2COF Flag. A Timer2 compare interrupt
(T2COM) will be generated only if the T2CIM bit is written to one, the Global Interrupt Flag in
SREG is written to one and the T2COF bit in T2IFR is set.
Bit 0 - T2OIM: Timer2 Overflow Interrupt Mask Bit
Writing this bit to one enables an interrupt on the T2OFF Flag. A Timer2 overflow interrupt
(T2OVF) will be generated only if the T2OIM bit is written to one, the Global Interrupt Flag in
SREG is written to one and the T2OFF bit in T2IFR is set.
3.13.5.14
Timer2 Mode Register A – T2MRA
Bits 7 to 6 – T2TP1..0: Timer 2 ToP Select Bits 1 to 0
The T2TP1 and T2TP0 bits select the fixed TOP compare value of theTimer2, shown in Table
Bit5 - T2CNC: Timer2 input Capture Noise Canceler Bit
Setting this bit (one) activates the Input Capture Noise Canceler. When the noise canceler is
activated, the input from the Input Capture pin (T2ICP, CLK
T1) is filtered. The filter function
requires four successive equal valued samples of the T2ICP pin for changing its output. The
Input Capture is therefore delayed by four counter clock (CL2) cycles when the noise canceler is
enabled.
Bits 4 to 3 – T2CE1..0: Timer2 Capture Edge Select Bits 1 to 0
The T2CE1 and T2CE0 bits select the edge from the capture input signal (T2ICP, CLK
T1) of
theTimer2, shown in Table 3-39.
Bit
765
432
10
T2TP1
T2TP0
T2CNC
T2CE1
T2CE0
T2CS2
T2CS1
T2CS0
T2MRA
Read/Write
R/W
Initial Value
000
00
Table 3-38.
Timer2 TOP Select Bit Description
T2TP1
T2TP0
Fixed TOP Value
0
Disable fixed value
0
1
0x00FF
1
0
0x01FF
1
0x03FF
Table 3-39.
Timer2 Capture Edge Select Bit Description
T2CE1
T2CE0
Input Capture Edge Signal (T2ICP) of Timer2
0
Disable edge detect
0
1
Rising edge
1
0
Falling edge
1
Both edge
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
A42MX16-1PL100M 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:40MX and 42MX FPGA Families
A42MX16-1PL84 功能描述:IC FPGA MX SGL CHIP 24K 84-PLCC RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:MX 標(biāo)準(zhǔn)包裝:40 系列:SX-A LAB/CLB數(shù):6036 邏輯元件/單元數(shù):- RAM 位總計:- 輸入/輸出數(shù):360 門數(shù):108000 電源電壓:2.25 V ~ 5.25 V 安裝類型:表面貼裝 工作溫度:0°C ~ 70°C 封裝/外殼:484-BGA 供應(yīng)商設(shè)備封裝:484-FPBGA（27X27）
A42MX16-1PL84I 功能描述:IC FPGA MX SGL CHIP 24K 84-PLCC RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:MX 標(biāo)準(zhǔn)包裝:40 系列:SX-A LAB/CLB數(shù):6036 邏輯元件/單元數(shù):- RAM 位總計:- 輸入/輸出數(shù):360 門數(shù):108000 電源電壓:2.25 V ~ 5.25 V 安裝類型:表面貼裝 工作溫度:0°C ~ 70°C 封裝/外殼:484-BGA 供應(yīng)商設(shè)備封裝:484-FPBGA（27X27）
A42MX16-1PL84M 制造商:Microsemi Corporation 功能描述:FPGA 42MX Family 24K Gates 608 Cells 119MHz/198MHz 0.45um Technology 3.3V/5V 84-Pin PLCC 制造商:Microsemi Corporation 功能描述:FPGA 24K GATES 608 CELLS 119MHZ/198MHZ 0.45UM 3.3V/5V 84PLCC - Rail/Tube 制造商:Microsemi Corporation 功能描述:IC FPGA 72 I/O 84PLCC 制造商:Microsemi Corporation 功能描述:IC FPGA MX SGL CHIP 24K 84-PLCC
A42MX16-1PLG84 功能描述:IC FPGA MX SGL CHIP 24K 84-PLCC RoHS:是 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:MX 標(biāo)準(zhǔn)包裝:40 系列:SX-A LAB/CLB數(shù):6036 邏輯元件/單元數(shù):- RAM 位總計:- 輸入/輸出數(shù):360 門數(shù):108000 電源電壓:2.25 V ~ 5.25 V 安裝類型:表面貼裝 工作溫度:0°C ~ 70°C 封裝/外殼:484-BGA 供應(yīng)商設(shè)備封裝:484-FPBGA（27X27）
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