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參數(shù)資料
| 型號： | A42MX16-1PQ100M |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | Octal D-type Edge-Triggered Flip-Flops With 3-State Outputs 20-TSSOP -40 to 85 |
| 中文描述： | 40MX和42MX FPGA系列 |
| 文件頁數(shù)： | 16/123頁 |
| 文件大?。?/td> | 854K |
| 代理商： | A42MX16-1PQ100M |
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40MX and 42MX FPGA Families
1-10
v6.0
Design Consideration
It is recommended to use a series 70
termination
resistor on every probe connector (SDI, SDO, MODE,
DCLK, PRA and PRB). The 70
series termination is used
to prevent data transmission corruption during probing
and reading back the checksum.
IEEE Standard 1149.1 Boundary Scan Test
(BST) Circuitry
42MX24 and 42MX36 devices are compatible with IEEE
Standard 1149.1 (informally known as Joint Testing
Action Group Standard or JTAG), which defines a set of
hardware architecture and mechanisms for cost-effective
board-level testing. The basic MX boundary-scan logic
circuit is composed of the TAP (test access port), TAP
controller, test data registers and instruction register
(
Figure 1-14 on page 1-11
). This circuit supports all
mandatory IEEE 1149.1 instructions (EXTEST, SAMPLE/
PRELOAD and BYPASS) and some optional instructions.
Table 3 on page 1-11
describes the ports that control
JTAG testing, while
Table 4 on page 1-11
describes the
test instructions supported by these MX devices.
Each test section is accessed through the TAP, which has
four associated pins: TCK (test clock input), TDI and TDO
(test data input and output), and TMS (test mode
selector).
The TAP controller is a four-bit state machine. The '1's
and '0's represent the values that must be present at TMS
at a rising edge of TCK for the given state transition to
occur. IR and DR indicate that the instruction register or
the data register is operating in that state.
The TAP controller receives two control inputs (TMS and
TCK) and generates control and clock signals for the rest
of the test logic architecture. On power-up, the TAP
controller enters the Test-Logic-Reset state. To guarantee
a reset of the controller from any of the possible states,
TMS must remain high for five TCK cycles.
42MX24 and 42MX36 devices support three types of test
data registers: bypass, device identification, and
boundary scan. The bypass register is selected when no
other register needs to be accessed in a device. This
speeds up test data transfer to other devices in a test
data path. The 32-bit device identification register is a
shift register with four fields (lowest significant byte
(LSB), ID number, part number and version). The
boundary-scan register observes and controls the state of
each I/O pin.
Figure 1-13
Silicon Explorer II Setup with 42MX
Table 2
Device Configuration Options for Probe Capability
Security Fuse(s)
Programmed
MODE
PRA, PRB
1
SDI, SDO, DCLK
1
No
LOW
User I/Os
2
User I/Os
2
No
HIGH
Probe Circuit Outputs
Probe Circuit Inputs
Yes
–
Probe Circuit Secured
Probe Circuit Secured
Notes:
1. Avoid using SDI, SDO, DCLK, PRA and PRB pins as input or bidirectional ports. Since these pins are active during probing, input
signals will not pass through these pins and may cause contention.
2. If no user signal is assigned to these pins, they will behave as unused I/Os in this mode. See the <zBlue>“Pin Descriptions” section
on page 77 for information on unused I/O pins.
42MX
Silicon
Explorer II
PRA
PRB
SDO
DCLK
SDI
MODE
Serial Connection
to Windows PC
16 Logic Analyzer Channels
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| A42MX16-1TQ100I | Octal D-type Edge-Triggered Flip-Flops With 3-State Outputs 20-TSSOP -40 to 85 |
| A42MX16-1TQ100M | Octal D-type Edge-Triggered Flip-Flops With 3-State Outputs 20-TSSOP -40 to 85 |
| A42MX16-1VQ100I | Octal D-type Edge-Triggered Flip-Flops With 3-State Outputs 20-TSSOP -40 to 85 |
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| A42MX16-2BG100M | Octal D-type Edge-Triggered Flip-Flops With 3-State Outputs 20-TSSOP -40 to 85 |
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