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參數(shù)資料
| 型號： | A42MX16-3PL100 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | 40MX and 42MX FPGA Families |
| 中文描述： | 40MX和42MX FPGA系列 |
| 文件頁數(shù)： | 20/120頁 |
| 文件大?。?/td> | 854K |
| 代理商： | A42MX16-3PL100 |
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116
4958B–AUTO–11/10
Atmel ATA6285/ATA6286 [Preliminary]
3.14.1.4
SPI Status Register – SPSR
Bit 7 - SPIF: SPI Interrupt Flag
When a serial transfer is complete, the SPIF Flag is set. An interrupt is generated if SPIE in
SPCR is set and global interrupts are enabled. If SS is an input and is driven low when the SPI is
in Master mode, this will also set the SPIF Flag. SPIF is cleared by hardware when executing the
corresponding interrupt handling vector. Alternatively, the SPIF bit is cleared by first reading the
SPI Status Register with SPIF set, then accessing the SPI Data Register (SPDR).
Bit 6 - WCOL: Write COLlision Flag
The WCOL bit is set if the SPI Data Register (SPDR) is written during a data transfer. The
WCOL bit (and the SPIF bit) is cleared by first reading the SPI Status Register with WCOL set,
and then accessing the SPI Data Register (SPDR).
Bit 5..1 - Res: Reserved Bits
These bits are reserved bits in the ATA6289 and will always read as zero.
Bit 0 - SPI2X: Double SPI Speed Bit
When this bit is written logic one the SPI speed (SCK Frequency) will be doubled when the SPI
is in Master mode (see Table 3-49). This means that the minimum SCK period will be two CPU
clock periods. When the SPI is configured as Slave, the SPI is only guaranteed to work at f
osc/4
or lower.
The SPI interface on the ATA6289 is also used for program memory and EEPROM downloading
or uploading. See Section 3.21.5 “Serial Downloading” on page 177 for serial programming and
verification.
Table 3-49.
Relationship Between SCK and the Oscillator Frequency f
OSC
SPI2X
SPR1
SPR0
SCK Frequency
00
0
f
OSC/4
00
1
f
OSC/16
01
0
f
OSC/64
01
1
f
OSC/128
10
0
f
OSC/2
10
1
f
OSC/8
11
0
f
OSC/32
11
1
f
OSC/64
Bit
7
6
5
432
10
SPIF
WCOL
-
SPI2X
SPSR
Read/Write
RR
RRR
RR
R/W
Initial Value
0
000
00
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| A42MX16-3PL100A | 40MX and 42MX FPGA Families |
| A42MX16-3PQ100A | 40MX and 42MX FPGA Families |
| A42MX16-3VQ100 | 40MX and 42MX FPGA Families |
| A42MX16-3VQ100A | 40MX and 42MX FPGA Families |
| A42MX16-3VQ100B | 40MX and 42MX FPGA Families |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| A42MX16-3PL100A | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:40MX and 42MX FPGA Families |
| A42MX16-3PL100B | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:40MX and 42MX FPGA Families |
| A42MX16-3PL100ES | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:40MX and 42MX FPGA Families |
| A42MX16-3PL100I | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:40MX and 42MX FPGA Families |
| A42MX16-3PL100M | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:40MX and 42MX FPGA Families |
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