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參數(shù)資料
| 型號(hào)： | A42MX16-3PL100 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | 40MX and 42MX FPGA Families |
| 中文描述： | 40MX和42MX FPGA系列 |
| 文件頁(yè)數(shù)： | 5/120頁(yè) |
| 文件大小： | 854K |
| 代理商： | A42MX16-3PL100 |
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102
4958B–AUTO–11/10
Atmel ATA6285/ATA6286 [Preliminary]
The two Compare Registers (T3CORA, T3CORB) and the Capture Register (T3ICR) are all
16-bit registers. Special procedures must be followed when accessing the 16-bit registers.
These procedures are described in Section 3.13.2 “Accessing 16-bit Registers” on page 70. The
Timer3 control, mode, mask and flag registers (T3CRA, T3CRB, T3MRA, T3MRB, T3IMR,
T3IFR) are all 8-bit registers and have no CPU access restrictions.
The comparator outputs are controlled by a control register (T3CRB) and contain mask bits for
the actions (counter reset, output toggle, single action) which can be triggered by a compare
match event or a capture event. The Output Compare Registers (T3CORA, T3CORB) are com-
pared with the Timer3/Counter3 value at every time. The counter can also be enabled to
execute single actions with one or both compare registers. If this mode is set the corresponding
compare match event is generated once a time after the counter starts.
The timer uses its compare registers alternately, if the T3AC bit is set at the T3CRA register.
After the timer has been activated, the first comparison is execute by the compare register A, the
second is execute by the compare register B, the third is execute by the compare register A and
so on as shown in Figure 3-48. This makes it easy to generate signals with constant periods and
variable duty cycle or to generate signals with variable pulse and space widths. If the T3AC bit is
cleared at the T3CRA register, the timer uses its compare registers not alternately for compare
matches.
Figure 3-48. Timer3 Alternate Compare Register Matches
This architecture enables the timer for various modes. The Timer3 operation modes and also the
modulator Output pin (T3O) is controlled by the T3MRB register.
Interrupt requests (shorten as Int. Req.) signals are all visible in the Timer Interrupt Flag Register
(T3IFR). All interrupts are individually masked with the Timer Interrupt Mask register (T3IMR).
The counter3 input clock (CL3) can be supplied via the I/O Clock (CLK
I/O), the external input
clock (T2I), the external input clock (T3I), the Timer0 output clock (CLK
T0), the Timer1 output
clock (CLK
T1), the Timer2 output clock (CLKT2), the integrated SRC output signal (SCH), or the
Timer clock (CLT).
T3CORA
inactive
T3CORB
active
Start (T3E)
or
Restart
T3CORA
active
Compare match
T3CORB
inactive
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| A42MX16-3PL100A | 40MX and 42MX FPGA Families |
| A42MX16-3PQ100A | 40MX and 42MX FPGA Families |
| A42MX16-3VQ100 | 40MX and 42MX FPGA Families |
| A42MX16-3VQ100A | 40MX and 42MX FPGA Families |
| A42MX16-3VQ100B | 40MX and 42MX FPGA Families |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| A42MX16-3PL100A | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:40MX and 42MX FPGA Families |
| A42MX16-3PL100B | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:40MX and 42MX FPGA Families |
| A42MX16-3PL100ES | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:40MX and 42MX FPGA Families |
| A42MX16-3PL100I | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:40MX and 42MX FPGA Families |
| A42MX16-3PL100M | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:40MX and 42MX FPGA Families |
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