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參數(shù)資料
| 型號： | A42MX24-1PQ100 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | 40MX and 42MX FPGA Families |
| 中文描述： | 40MX和42MX FPGA系列 |
| 文件頁數(shù)： | 60/93頁 |
| 文件大?。?/td> | 854K |
| 代理商： | A42MX24-1PQ100 |
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63
Data Device Corporation
www.ddc-web.com
BU-6474X/6484X/6486X
J-07/05-0
TABLE 62. PROCESSOR INTERFACE CONTROL (CONT.)
SIGNAL NAME
DESCRIPTION
BU-64840B3
BU-64860B3
BALL
BU-64743B8
BU-64843B8
BU-64863B8
BALL
POL_SEL (I) /
DTACK (O)
N9
Data Transfer Acknowledge or Polarity Select.
In 16-bit buffered mode, if POL_SEL is connected to logic "1", RD/WR should be
asserted high (logic "1") for a read operation and low (logic "0") for a write opera-
tion. In 16-bit buffered mode, if POL_SEL is connected to logic "0", RD/WR should
be asserted low (logic "0") for a read operation and high (logic "1") for a write
operation.
In 8-bit buffered mode (TRANSPARENT/ BUFFERED = "0" and 16/8 = "0"),
POL_SEL input signal used to control the logic sense of the MSB/LSB signal. If
POL_SEL is connected to logic "0", MSB/LSB should be asserted low (logic "0")
to indicate the transfer of the least significant byte and high (logic "1") to indicate
the transfer of the most significant byte. If POL_SEL is connected to logic "1",
MSB/LSB should be asserted high (logic "1") to indicate the transfer of the least
significant byte and low (logic "0") to indicate the transfer of the most significant
byte.
In transparent mode, active low output signal (DTACK) used to indicate accep-
tance of the processor/RAM interface bus in response to a data transfer grant
(DTGRT). Mark3 RAM transfers over A15-A0 and D15-D0 will be framed by the
time that DTACK is asserted low.
V8
TRIG_SEL (I) /
MEMENA_IN (I)
L11
Memory Enable or Trigger Select input.
In 8-bit buffered mode, input signal (TRIG-SEL) used to select the order in which
byte pairs are transferred to or from the Mark3 by the host processor. In the 8-bit
buffered mode, TRIG_SEL should be asserted high (logic 1) if the byte order for
both read operations and write operations is MSB followed by LSB. TRIG_SEL
should be asserted low (logic 0) if the byte order for both read operations and
write operations is LSB followed by MSB.
This signal has no operation in the 16-bit buffered mode (it does not need to be
connected).
In transparent mode, active low input MEMENA_IN, used as a Chip Select (CS)
input to the Mark3's internal shared RAM. If only internal RAM is used, should be
connected directly to the output of a gate that is OR'ing the DTACK and IOEN out-
put signals.
N17
MEM / REG(I)
C11
Memory/Register.
Generally connected to either a CPU address line or address decoder output.
Selects between memory access (MEM/REG = "1") or register access (MEM/REG
= "0").
A6
BALL GRID ARRAY PACKAGE - SIGNAL DESCRIPTIONS BY FUNCTIONAL GROUPS (CONT.)
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| A42MX02-1PQ100A | Audio Transformer; Power Rating:1W; Mounting Type:PCB Surface; External Depth:1.125"; External Height:1.125"; External Width:1.375"; Frequency Response Max:15kHz; Frequency Response Min:200Hz; Leaded Process Compatible:Yes |
| A42MX04-1PQ100A | Line Matching Transformer; Leaded Process Compatible:Yes; Insertion Loss:0.8dBA; Peak Reflow Compatible (260 C):Yes |
| A42MX09-1PQ100A | TRANSF 900 OHM SEC. 0MA DC TEL |
| A42MX16-1PQ100A | 40MX and 42MX FPGA Families |
| A42MX24-1PQ100A | TRANSF 4000 OHM PRI. 0MA DC TEL |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| A42MX24-1PQ160 | 功能描述:IC FPGA MX SGL CHIP 36K 160-PQFP RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:MX 產(chǎn)品培訓模塊:Three Reasons to Use FPGA's in Industrial Designs Cyclone IV FPGA Family Overview 特色產(chǎn)品:Cyclone? IV FPGAs 標準包裝:60 系列:CYCLONE® IV GX LAB/CLB數(shù):9360 邏輯元件/單元數(shù):149760 RAM 位總計:6635520 輸入/輸出數(shù):270 門數(shù):- 電源電壓:1.16 V ~ 1.24 V 安裝類型:表面貼裝 工作溫度:0°C ~ 85°C 封裝/外殼:484-BGA 供應(yīng)商設(shè)備封裝:484-FBGA（23x23） |
| A42MX24-1PQ160I | 功能描述:IC FPGA MX SGL CHIP 36K 160-PQFP RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:MX 產(chǎn)品培訓模塊:Three Reasons to Use FPGA's in Industrial Designs Cyclone IV FPGA Family Overview 特色產(chǎn)品:Cyclone? IV FPGAs 標準包裝:60 系列:CYCLONE® IV GX LAB/CLB數(shù):9360 邏輯元件/單元數(shù):149760 RAM 位總計:6635520 輸入/輸出數(shù):270 門數(shù):- 電源電壓:1.16 V ~ 1.24 V 安裝類型:表面貼裝 工作溫度:0°C ~ 85°C 封裝/外殼:484-BGA 供應(yīng)商設(shè)備封裝:484-FBGA（23x23） |
| A42MX24-1PQ160M | 制造商:Microsemi Corporation 功能描述:FPGA 36K GATES 912 CELLS 0.45UM 3.3V/5V 160PQFP - Trays 制造商:Microsemi Corporation 功能描述:IC FPGA MX SGL CHIP 36K 160-PQFP 制造商:Microsemi Corporation 功能描述:IC FPGA 125 I/O 160PQFP |
| A42MX24-1PQ208 | 功能描述:IC FPGA MX SGL CHIP 36K 208-PQFP RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:MX 產(chǎn)品培訓模塊:Three Reasons to Use FPGA's in Industrial Designs Cyclone IV FPGA Family Overview 特色產(chǎn)品:Cyclone? IV FPGAs 標準包裝:60 系列:CYCLONE® IV GX LAB/CLB數(shù):9360 邏輯元件/單元數(shù):149760 RAM 位總計:6635520 輸入/輸出數(shù):270 門數(shù):- 電源電壓:1.16 V ~ 1.24 V 安裝類型:表面貼裝 工作溫度:0°C ~ 85°C 封裝/外殼:484-BGA 供應(yīng)商設(shè)備封裝:484-FBGA（23x23） |
| A42MX24-1PQ208I | 功能描述:IC FPGA MX SGL CHIP 36K 208-PQFP RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:MX 產(chǎn)品培訓模塊:Three Reasons to Use FPGA's in Industrial Designs Cyclone IV FPGA Family Overview 特色產(chǎn)品:Cyclone? IV FPGAs 標準包裝:60 系列:CYCLONE® IV GX LAB/CLB數(shù):9360 邏輯元件/單元數(shù):149760 RAM 位總計:6635520 輸入/輸出數(shù):270 門數(shù):- 電源電壓:1.16 V ~ 1.24 V 安裝類型:表面貼裝 工作溫度:0°C ~ 85°C 封裝/外殼:484-BGA 供應(yīng)商設(shè)備封裝:484-FBGA（23x23） |
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