- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄298744 > A42MX24-2TQ100B (Electronic Theatre Controls, Inc.) 40MX and 42MX FPGA Families PDF資料下載
參數(shù)資料
| 型號： | A42MX24-2TQ100B |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | 40MX and 42MX FPGA Families |
| 中文描述： | 40MX和42MX FPGA系列 |
| 文件頁數(shù)： | 27/93頁 |
| 文件大小： | 854K |
| 代理商： | A42MX24-2TQ100B |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁當前第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁
33
Data Device Corporation
www.ddc-web.com
BU-6474X/6484X/6486X
J-07/05-0
RT COMMAND ILLEGALIZATION
The Mini-ACE Mark3 provides an internal mechanism for RT
Command Word illegalizing. By means of a 256-word area in
shared RAM, the host processor may designate that any mes-
sage be illegalized, based on the command word T/R bit, sub-
address, and word count/mode code fields. The Mini-ACE Mark3
illegalization scheme provides the maximum in flexibility, allow-
ing any subset of the 4096 possible combinations of broad-
cast/own address, T/R bit, subaddress, and word count/mode
code to be illegalized.
The address map of the Mini-ACE Mark3's illegalizing table is
illustrated in TABLE 41.
BUSY BIT
The Mini-ACE Mark3 RT provides two different methods for set-
ting the Busy status word bit: (1) globally, by means of
Configuration Register #1; or (2) on a T/R-bit/subaddress basis,
by means of a RAM lookup table. If the host CPU asserts the
BUSY bit to logic “0” in Configuration Register #1, the Mini-ACE
Mark3 RT will respond to all non-broadcast commands with the
Busy bit set in its RT Status Word.
Alternatively, there is a Busy lookup table in the Mini-ACE Mark3
shared RAM. By means of this table, it is possible for the host
processor to set the busy bit for any selectable subset of the 128
combinations of broadcast/own address, T/R bit, and subaddress.
If the busy bit is set for a transmit command, the Mini-ACE Mark3
RT will respond with the busy bit set in the status word, but will
not transmit any data words. If the busy bit is set for a receive
command, the RT will also respond with the busy status bit set.
There are two programmable options regarding the reception of
data words for a non-mode code receive command for which the
RT is busy: (1) to transfer the received data words to shared
RAM; or (2) to not transfer the data words to shared RAM.
RT ADDRESS
The Mini-ACE Mark3 offers several different options for desig-
nating the Remote Terminal address. These include the follow-
ing: (1) hardwired, by means of the 5 RT ADDRESS inputs, and
the RT ADDRESS PARITY input; (2) by means of the RT
ADDRESS (and PARITY) inputs, but latched via hardware, on
the rising edge of the RT_AD_LAT input signal; (3) input by
means of the RT ADDRESS (and PARITY) inputs, but latched via
host software; and (4) software programmable, by means of an
internal register. In all four configurations, the RT address is
readable by the host processor.
RT BUILT-IN-TEST (BIT) WORD
The bit map for the Mini-ACE Mark3's internal RT Built-in-Test
(BIT) Word is indicated in TABLE 42.
RT AUTO-BOOT OPTION
If utilized, the RT pin-programmable auto-boot option allows the
Mini-ACE Mark3 RT to automatically initialize as an active
COMMAND WORD CONTENTS ERROR
0 (LSB)
RT-to-RT 2ND COMMAND WORD ERROR
1
RT-to-RT NO RESPONSE ERROR
2
TRANSMITTER SHUTDOWN B
RT-to-RT GAP / SYNC ADDRESS ERROR
3
PARITY / MANCHESTER ERROR RECEIVED
4
INCORRECT SYNC RECEIVED
5
LOW WORD COUNT
6
HIGH WORD COUNT
7
BIT TEST FAILURE
8
TERMINAL FLAG INHIBITED
9
TRANSMITTER SHUTDOWN A
10
HANDSHAKE FAILURE
12
LOOP TEST FAILURE A
13
LOOP TEST FAILURE B
14
TRANSMITTER TIMEOUT
15(MSB)
DESCRIPTION
BIT
11
TABLE 42. RT BIT WORD
remote terminal with the Busy status word bit set to logic "1"
immediately following power turn-on. This is a useful feature for
MIL-STD-1760 applications, in which the RT is required to be
responding within 150 ms after power-up. This feature is avail-
able for versions of the Mini-ACE Mark3 with 4K words of RAM.
OTHER RT FEATURES
The Mini-ACE Mark3 includes options for the Terminal flag sta-
tus word bit to be set either under software control and/or auto-
matically following a failure of the loopback self-test. Other soft-
ware programmable RT options include software programmable
RT status and RT BIT words, automatic clearing of the Service
Request bit following receipt of a Transmit vector word mode
command, options regarding Data Word transfers for the Busy
and Message error (illegal) Status word bits, and options for the
handling of 1553A and reserved mode codes.
MONITOR ARCHITECTURE
The Mini-ACE Mark3 includes three monitor modes:
(1) A Word Monitor mode
(2) A selective message monitor mode
(3) A combined RT/message monitor mode
For new applications, it is recommended that the selective mes-
sage monitor mode be used, rather than the word monitor mode.
Besides providing monitor filtering based on RT address, T/R bit,
and subaddress, the message monitor eliminates the need to
determine the start and end of messages by software.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| A42MX24-2VQ100 | 40MX and 42MX FPGA Families |
| A42MX24-2VQ100A | 40MX and 42MX FPGA Families |
| A42MX24-2VQ100B | 40MX and 42MX FPGA Families |
| A42MX24-3PQ100B | 40MX and 42MX FPGA Families |
| A42MX24-3BG100 | 40MX and 42MX FPGA Families |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| A42MX24-2TQ176 | 功能描述:IC FPGA MX SGL CHIP 36K 176-TQFP RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:MX 產(chǎn)品培訓(xùn)模塊:Three Reasons to Use FPGA's in Industrial Designs Cyclone IV FPGA Family Overview 特色產(chǎn)品:Cyclone? IV FPGAs 標準包裝:60 系列:CYCLONE® IV GX LAB/CLB數(shù):9360 邏輯元件/單元數(shù):149760 RAM 位總計:6635520 輸入/輸出數(shù):270 門數(shù):- 電源電壓:1.16 V ~ 1.24 V 安裝類型:表面貼裝 工作溫度:0°C ~ 85°C 封裝/外殼:484-BGA 供應(yīng)商設(shè)備封裝:484-FBGA（23x23） |
| A42MX24-2TQ176I | 功能描述:IC FPGA MX SGL CHIP 36K 176-TQFP RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:MX 產(chǎn)品培訓(xùn)模塊:Three Reasons to Use FPGA's in Industrial Designs Cyclone IV FPGA Family Overview 特色產(chǎn)品:Cyclone? IV FPGAs 標準包裝:60 系列:CYCLONE® IV GX LAB/CLB數(shù):9360 邏輯元件/單元數(shù):149760 RAM 位總計:6635520 輸入/輸出數(shù):270 門數(shù):- 電源電壓:1.16 V ~ 1.24 V 安裝類型:表面貼裝 工作溫度:0°C ~ 85°C 封裝/外殼:484-BGA 供應(yīng)商設(shè)備封裝:484-FBGA（23x23） |
| A42MX24-2TQG176 | 功能描述:IC FPGA MX SGL CHIP 36K 176-TQFP RoHS:是 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:MX 產(chǎn)品培訓(xùn)模塊:Three Reasons to Use FPGA's in Industrial Designs Cyclone IV FPGA Family Overview 特色產(chǎn)品:Cyclone? IV FPGAs 標準包裝:60 系列:CYCLONE® IV GX LAB/CLB數(shù):9360 邏輯元件/單元數(shù):149760 RAM 位總計:6635520 輸入/輸出數(shù):270 門數(shù):- 電源電壓:1.16 V ~ 1.24 V 安裝類型:表面貼裝 工作溫度:0°C ~ 85°C 封裝/外殼:484-BGA 供應(yīng)商設(shè)備封裝:484-FBGA（23x23） |
| A42MX24-2TQG176I | 功能描述:IC FPGA MX SGL CHIP 36K 176-TQFP RoHS:是 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:MX 產(chǎn)品培訓(xùn)模塊:Three Reasons to Use FPGA's in Industrial Designs Cyclone IV FPGA Family Overview 特色產(chǎn)品:Cyclone? IV FPGAs 標準包裝:60 系列:CYCLONE® IV GX LAB/CLB數(shù):9360 邏輯元件/單元數(shù):149760 RAM 位總計:6635520 輸入/輸出數(shù):270 門數(shù):- 電源電壓:1.16 V ~ 1.24 V 安裝類型:表面貼裝 工作溫度:0°C ~ 85°C 封裝/外殼:484-BGA 供應(yīng)商設(shè)備封裝:484-FBGA（23x23） |
| A42MX24-3PL84 | 功能描述:IC FPGA MX SGL CHIP 36K 84-PLCC RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:MX 產(chǎn)品培訓(xùn)模塊:Three Reasons to Use FPGA's in Industrial Designs Cyclone IV FPGA Family Overview 特色產(chǎn)品:Cyclone? IV FPGAs 標準包裝:60 系列:CYCLONE® IV GX LAB/CLB數(shù):9360 邏輯元件/單元數(shù):149760 RAM 位總計:6635520 輸入/輸出數(shù):270 門數(shù):- 電源電壓:1.16 V ~ 1.24 V 安裝類型:表面貼裝 工作溫度:0°C ~ 85°C 封裝/外殼:484-BGA 供應(yīng)商設(shè)備封裝:484-FBGA（23x23） |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。