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參數(shù)資料
| 型號： | A42MX24-2VQ100 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | 40MX and 42MX FPGA Families |
| 中文描述： | 40MX和42MX FPGA系列 |
| 文件頁數(shù)： | 61/93頁 |
| 文件大小： | 854K |
| 代理商： | A42MX24-2VQ100 |
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64
Data Device Corporation
www.ddc-web.com
BU-6474X/6484X/6486X
J-07/05-0
TABLE 62 . PROCESSOR INTERFACE CONTROL (CONT.)
SIGNAL NAME
DESCRIPTION
BU-64840B3
BU-64860B3
BALL
BU-64743B8
BU-64843B8
BU-64863B8
BALL
SSFLAG (I) /
EXT_TRIG(I)
J8
Subsystem Flag (RT) or External Trigger (BC/Word Monitor) input.
In RT mode, if this input is asserted low, the Subsystem Flag bit will be set in the
Mark3's RT Status Word. If the SSFLAG input is logic "0" while bit 8 of
Configuration Register #1 has been programmed to logic "1" (cleared), the
Subsystem Flag RT Status Word bit will become logic "1," but bit 8 of
Configuration Register #1, SUBSYSTEM FLAG, will return logic "1" when read.
That is, the sense on the SSFLAG input has no effect on the SUBSYSTEM FLAG
register bit.
In the non-enhanced BC mode, this signal operates as an External Trigger input.
In BC mode, if the external BC Start option is enabled (bit 7 of Configuration
Register #1), a low to high transition on this input will issue a BC Start command,
starting execution of the current BC frame.
In the enhanced BC mode, during the execution of a Wait for External Trigger
(WTG) instruction, the Mark3 BC will wait for a low-to-high transition on
EXT_TRIG before proceeding to the next instruction.
In the Word Monitor mode, if the external trigger is enabled (bit 7 of Configuration
Register #1), a low to high transition on this input will initiate a monitor start.
This input has no effect in Message Monitor mode.
R8
TRANSPARENT/
BUFFERED (I)
D16
Used to select between the buffered mode (when strapped to logic "0") and trans-
parent/DMA mode (when strapped to logic "1") for the host processor interface.
D17
READYD (O)
C15
Handshake output to host processor.
For a nonzero wait state read access, READYD is asserted at the end of a host
transfer cycle to indicate that data is available to be read on D15 through D0 when
asserted (low). For a nonzero wait state write cycle, READYD is asserted at the
end of the cycle to indicate that data has been transferred to a register or RAM
location. For both nonzero wait reads and writes, the host must assert STRBD low
until READYD is asserted low.
In the (buffered) zero wait state mode, this output is normally logic "1", indicating
that the Mark3 is in a state ready to accept a subsequent host transfer cycle. In
zero wait mode, READYD will transition from high to low during (or just after) a
host transfer cycle, when the Mark3 initiates its internal transfer to or from regis-
ters or internal RAM. When the Mark3 completes its internal transfer, READYD
returns to logic "1", indicating it is ready for the host to initiate a subsequent trans-
fer cycle.
B15
IOEN(O)
C14
I/O Enable.
Tri-state control for external address and data buffers. Generally not used in
buffered mode. When low, indicates that the Mark3 is currently performing a host
access to an internal register, or internal (for transparent mode) external RAM. In
transparent mode, IOEN (low) should be used to enable external address and
data bus tri-state buffers.
A15
BALL GRID ARRAY PACKAGE - SIGNAL DESCRIPTIONS BY FUNCTIONAL GROUPS (CONT.)
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| A42MX24-2VQ100A | 40MX and 42MX FPGA Families |
| A42MX24-2VQ100B | 40MX and 42MX FPGA Families |
| A42MX24-3PQ100B | 40MX and 42MX FPGA Families |
| A42MX24-3BG100 | 40MX and 42MX FPGA Families |
| A42MX24-3PL100 | 40MX and 42MX FPGA Families |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| A42MX24-3PL84 | 功能描述:IC FPGA MX SGL CHIP 36K 84-PLCC RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:MX 產(chǎn)品培訓(xùn)模塊:Three Reasons to Use FPGA's in Industrial Designs Cyclone IV FPGA Family Overview 特色產(chǎn)品:Cyclone? IV FPGAs 標(biāo)準(zhǔn)包裝:60 系列:CYCLONE® IV GX LAB/CLB數(shù):9360 邏輯元件/單元數(shù):149760 RAM 位總計(jì):6635520 輸入/輸出數(shù):270 門數(shù):- 電源電壓:1.16 V ~ 1.24 V 安裝類型:表面貼裝 工作溫度:0°C ~ 85°C 封裝/外殼:484-BGA 供應(yīng)商設(shè)備封裝:484-FBGA（23x23） |
| A42MX24-3PL84I | 功能描述:IC FPGA MX SGL CHIP 36K 84-PLCC RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:MX 產(chǎn)品培訓(xùn)模塊:Three Reasons to Use FPGA's in Industrial Designs Cyclone IV FPGA Family Overview 特色產(chǎn)品:Cyclone? IV FPGAs 標(biāo)準(zhǔn)包裝:60 系列:CYCLONE® IV GX LAB/CLB數(shù):9360 邏輯元件/單元數(shù):149760 RAM 位總計(jì):6635520 輸入/輸出數(shù):270 門數(shù):- 電源電壓:1.16 V ~ 1.24 V 安裝類型:表面貼裝 工作溫度:0°C ~ 85°C 封裝/外殼:484-BGA 供應(yīng)商設(shè)備封裝:484-FBGA（23x23） |
| A42MX24-3PLG84 | 功能描述:IC FPGA MX SGL CHIP 36K 84-PLCC RoHS:是 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:MX 產(chǎn)品培訓(xùn)模塊:Three Reasons to Use FPGA's in Industrial Designs Cyclone IV FPGA Family Overview 特色產(chǎn)品:Cyclone? IV FPGAs 標(biāo)準(zhǔn)包裝:60 系列:CYCLONE® IV GX LAB/CLB數(shù):9360 邏輯元件/單元數(shù):149760 RAM 位總計(jì):6635520 輸入/輸出數(shù):270 門數(shù):- 電源電壓:1.16 V ~ 1.24 V 安裝類型:表面貼裝 工作溫度:0°C ~ 85°C 封裝/外殼:484-BGA 供應(yīng)商設(shè)備封裝:484-FBGA（23x23） |
| A42MX24-3PLG84I | 功能描述:IC FPGA MX SGL CHIP 36K 84-PLCC RoHS:是 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:MX 產(chǎn)品培訓(xùn)模塊:Three Reasons to Use FPGA's in Industrial Designs Cyclone IV FPGA Family Overview 特色產(chǎn)品:Cyclone? IV FPGAs 標(biāo)準(zhǔn)包裝:60 系列:CYCLONE® IV GX LAB/CLB數(shù):9360 邏輯元件/單元數(shù):149760 RAM 位總計(jì):6635520 輸入/輸出數(shù):270 門數(shù):- 電源電壓:1.16 V ~ 1.24 V 安裝類型:表面貼裝 工作溫度:0°C ~ 85°C 封裝/外殼:484-BGA 供應(yīng)商設(shè)備封裝:484-FBGA（23x23） |
| A42MX24-3PQ160 | 功能描述:IC FPGA MX SGL CHIP 36K 160-PQFP RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:MX 產(chǎn)品培訓(xùn)模塊:Three Reasons to Use FPGA's in Industrial Designs Cyclone IV FPGA Family Overview 特色產(chǎn)品:Cyclone? IV FPGAs 標(biāo)準(zhǔn)包裝:60 系列:CYCLONE® IV GX LAB/CLB數(shù):9360 邏輯元件/單元數(shù):149760 RAM 位總計(jì):6635520 輸入/輸出數(shù):270 門數(shù):- 電源電壓:1.16 V ~ 1.24 V 安裝類型:表面貼裝 工作溫度:0°C ~ 85°C 封裝/外殼:484-BGA 供應(yīng)商設(shè)備封裝:484-FBGA（23x23） |
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