參數(shù)資料
型號: A42MX24-2VQ100
廠商: Electronic Theatre Controls, Inc.
英文描述: 40MX and 42MX FPGA Families
中文描述: 40MX和42MX FPGA系列
文件頁數(shù): 66/93頁
文件大?。?/td> 854K
代理商: A42MX24-2VQ100
69
Data Device Corporation
www.ddc-web.com
BU-6474X/6484X/6486X
J-07/05-0
41
PIN
DB06
42
DB08
43
3.3V_LOGIC
GND_LOGIC
44
DB05
45
DB03
46
47
DB02
48
DB00
49
RTAD1
50
RTADP
51
FUNCTION
DB04
52
DB01
DB09
53
DB14
54
55
DB12
56
DB13
57
DB07
TX_INH_A
IOEN
INT
61
TRANS/BUFF
63
64
65
GND_LOGIC
3.3V_LOGIC
69
70
RD/WR
71
A09
75
A12* or A12/RTBOOT**
76
A05
DB10
DB15
DB11
58
59
60
SELECT
READYD
62
66
STRBD
TX_INH_B
67
68
A15* or A15/CLK_SEL_1**
MSB/LSB/DTGRT
72
73
74
A11
1
A10
TXDATA_A
PIN
RXDATA_A ***
2
FUNCTION
3
4
TXDATA_A
5
MEM/REG
6
A08
7
RXDATA_A
TXINH_B_OUT
+3.3V_LOGIC
8
9
10
TXINH_A_OUT
11
TABLE 67. MINI-ACE MARK3 BU-64XX3F/G0 (TRANSCEIVERLESS) VERSION PINOUTS
A07
12
A03
13
UPADDREN** or NC*
14
TXDATA_B
15
RXDATA_B ***
TXDATA_B
A00
16
17
18
A02
19
ADDR_LAT/MEMOE
20
RXDATA_B
21
GND_LOGIC
TAG_CLK
RTAD2
22
23
24
MSTCLR
25
CLOCK_IN
26
A06
ZEROWAIT/MEMWR
27
28
16/8/DTREQ
29
3.3V_LOGIC
30
GND_LOGIC
INCMD/MCRST
31
32
A01
33
TRIG_SEL/MEMENA_IN
34
POL_SEL/DTACK
RT_AD_LAT
35
36
SSFLAG/EXT_TRIG
37
A13* or A13/+3.3V_LOGIC**
77
A04
78
RTAD0
38
RTAD3
39
GND_LOGIC
79
A14* or A14/CLK_SEL_0**
80
RTAD4
40
* Applicable for 64K RAM option.
** Applicable for 4K RAM option.
*** Standard transceiverless parts have their receiver inputs internally strapped for single-ended operation. The RXDATAx pins are connected to inputs that are not enabled.
相關(guān)PDF資料
PDF描述
A42MX24-2VQ100A 40MX and 42MX FPGA Families
A42MX24-2VQ100B 40MX and 42MX FPGA Families
A42MX24-3PQ100B 40MX and 42MX FPGA Families
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