參數(shù)資料
型號： A42MX36-BG272A
元件分類： FPGA
英文描述： FPGA, 54000 GATES, PBGA272
封裝： PLASTIC, BGA-272
文件頁數(shù)： 33/76頁
文件大?。?/td> 429K
代理商： A42MX36-BG272A
MX Automotive Family FPGAs
v2.0
1-33
tINGH
G to Y HIGH
2.5
ns
tINGL
G to Y LOW
2.5
ns
Input Module Predicted Routing Delays2
tIRD1
FO=1 Routing Delay
3.2
ns
tIRD2
FO=2 Routing Delay
3.6
ns
tIRD3
FO=3 Routing Delay
4.1
ns
tIRD4
FO=4 Routing Delay
4.6
ns
tIRD8
FO=8 Routing Delay
6.3
ns
Global Clock Network
tCKH
Input LOW to HIGH
FO = 32
FO = 384
4.6
5.1
ns
tCKL
Input HIGH to LOW
FO = 32
FO = 384
6.6
7.8
ns
tPWH
Minimum Pulse Width HIGH
FO = 32
FO = 384
5.5
6.3
ns
tPWL
Minimum Pulse Width LOW
FO = 32
FO = 384
5.5
6.3
ns
tCKSW
Maximum Skew
FO = 32
FO = 384
0.6
ns
tSUEXT
Input Latch External Set-Up
FO = 32
FO = 384
0.0
ns
tHEXT
Input Latch External Hold
FO = 32
FO = 384
4.8
5.5
ns
tP
Minimum Period
FO = 32
FO = 384
6.8
7.5
ns
fMAX
Maximum Frequency
FO = 32
FO = 384
202
183
MHz
TTL Output Module Timing5
tDLH
Data-to-Pad HIGH
4.4
ns
tDHL
Data-to-Pad LOW
5.2
ns
Table 1-8 A42MX16 Timing Characteristics (Nominal 5.0V Operation)
Worst-Case Automotive Conditions, VCC = 4.75V, TJ = 125°C (Continued)
‘Std’ Speed
Parameter
Description
Min.
Max.
Units
1. For dual-module macros, use tPD1 + tRD1 + tPDn, tCO + tRD1 + tPDn, or tPD1 + tRD1 + tSUD, point and position whichever is
appropriate.
2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating
device performance. Post-route timing analysis or simulation is required to determine actual performance.
3. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules can be
obtained from the Timer utility.
4. Set-up and hold timing parameters for the input buffer latch are defined with respect to the PAD and the D input. External setup/
hold timing parameters must account for delay from an external PAD signal to the G inputs. Delay from an external PAD signal to
the G input subtracts (adds) to the internal setup (hold) time.
5. Delays based on 35 pF loading.
相關(guān)PDF資料
PDF描述
A42MX36-BGG272A FPGA, 54000 GATES, PBGA272
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A42MX36-CQ256A FPGA, 54000 GATES, CQFP256
A42MX36-1RQ208I FPGA, 2438 CLBS, 36000 GATES, 91 MHz, PQFP208
A42MX36-1RQ208 FPGA, 2438 CLBS, 36000 GATES, 91 MHz, PQFP208
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
A42MX36-BG272I 功能描述:IC FPGA MX SGL CHIP 54K 272-PBGA RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:MX 標(biāo)準(zhǔn)包裝:1 系列:ProASICPLUS LAB/CLB數(shù):- 邏輯元件/單元數(shù):- RAM 位總計(jì):129024 輸入/輸出數(shù):248 門數(shù):600000 電源電壓:2.3 V ~ 2.7 V 安裝類型:表面貼裝 工作溫度:- 封裝/外殼:352-BFCQFP，帶拉桿 供應(yīng)商設(shè)備封裝:352-CQFP（75x75）
A42MX36-BG272M 制造商:Microsemi Corporation 功能描述:FPGA 42MX Family 54K Gates 1184 Cells 79MHz/131MHz 0.45um Technology 3.3V/5V 272-Pin BGA 制造商:Microsemi Corporation 功能描述:FPGA 54K GATES 1184 CELLS 79MHZ/131MHZ 0.45UM 3.3V/5V 272BGA - Trays 制造商:Microsemi Corporation 功能描述:IC FPGA 202 I/O 272PBGA 制造商:Microsemi Corporation 功能描述:IC FPGA MX SGL CHIP 54K 272-PBGA
A42MX36-BGG272 功能描述:IC FPGA MX SGL CHIP 54K 272-PBGA RoHS:是 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:MX 產(chǎn)品培訓(xùn)模塊:Three Reasons to Use FPGA's in Industrial Designs Cyclone IV FPGA Family Overview 特色產(chǎn)品:Cyclone? IV FPGAs 標(biāo)準(zhǔn)包裝:60 系列:CYCLONE® IV GX LAB/CLB數(shù):9360 邏輯元件/單元數(shù):149760 RAM 位總計(jì):6635520 輸入/輸出數(shù):270 門數(shù):- 電源電壓:1.16 V ~ 1.24 V 安裝類型:表面貼裝 工作溫度:0°C ~ 85°C 封裝/外殼:484-BGA 供應(yīng)商設(shè)備封裝:484-FBGA（23x23）
A42MX36-BGG272I 功能描述:IC FPGA MX SGL CHIP 54K 272-PBGA RoHS:是 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:MX 標(biāo)準(zhǔn)包裝:1 系列:ProASICPLUS LAB/CLB數(shù):- 邏輯元件/單元數(shù):- RAM 位總計(jì):129024 輸入/輸出數(shù):248 門數(shù):600000 電源電壓:2.3 V ~ 2.7 V 安裝類型:表面貼裝 工作溫度:- 封裝/外殼:352-BFCQFP，帶拉桿 供應(yīng)商設(shè)備封裝:352-CQFP（75x75）
A42MX36-BGG272M 制造商:Microsemi Corporation 功能描述:FPGA 42MX Family 54K Gates 1184 Cells 79MHz/131MHz 0.45um Technology 3.3V/5V 272-Pin BGA 制造商:Microsemi Corporation 功能描述:FPGA 54K GATES 1184 CELLS 79MHZ/131MHZ 0.45UM 3.3V/5V 272BGA - Trays 制造商:Microsemi Corporation 功能描述:IC FPGA 202 I/O 272PBGA
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