Table 1-19 DC Specification" />
參數(shù)資料
型號: A42MX36-FBG272
廠商: Microsemi SoC
文件頁數(shù): 64/142頁
文件大?。?/td> 0K
描述: IC FPGA MX SGL CHIP 54K 272-PBGA
標準包裝: 40
系列: MX
RAM 位總計: 2560
輸入/輸出數(shù): 202
門數(shù): 54000
電源電壓: 3 V ~ 3.6 V,4.75 V ~ 5.25 V
安裝類型: 表面貼裝
工作溫度: 0°C ~ 70°C
封裝/外殼: 272-BBGA
供應商設(shè)備封裝: 272-PBGA(27x27)
40MX and 42MX FPGA Families
1- 24
R e v i sio n 1 1
Output Drive Characteristics for 3.3 V PCI Signaling
Table 1-19 DC Specification (3.3 V PCI Signaling)1
PCI
MX
Symbol
Parameter
Condition
Min.
Max.
Min.
Max.
Units
VCCI
Supply Voltage for I/Os
3.0
3.6
3.0
3.6
V
VIH
Input High Voltage
0.5
VCC + 0.5
0.5
VCCI + 0.3
V
VIL
Input Low Voltage
–0.5
0.8
–0.3
0.8
V
IIH
Input High Leakage Current
VIN = 2.7V
70
10
A
IIL
Input Leakage Current
–70
–10
A
VOH
Output High Voltage
IOUT = –2 mA
0.9
3.3
V
VOL
Output Low Voltage
IOUT = 3 mA, 6 mA
0.1
0.1 VCCI
V
CIN
Input Pin Capacitance
10
pF
CCLK
CLK Pin Capacitance
5
12
10
pF
LPIN
Pin Inductance
20
< 8 nH3
nH
Notes:
1. PCI Local Bus Specification, Version 2.1, Section 4.2.2.1.
2. Maximum rating for VCCI –0.5V to 7.0V.
3. Dependent upon the chosen package. PCI recommends QFP and BGA packaging to reduce pin inductance and
capacitance.
Table 1-20 AC Specifications for (3.3 V PCI Signaling)*
PCI
MX
Symbol
Parameter
Condition
Min.
Max.
Min.
Max.
Units
ICL
Low Clamp Current
–5 < VIN
–1
–25 + (VIN +1) /0.015
–60
–10
mA
Slew (r) Output Rise Slew Rate
0.2 V to 0.6 V load
1
4
1.8
2.8
V/ns
Slew (f)
Output Fall Slew Rate
0.6 V to 0.2 V load
1
4
2.8
4.0
V/ns
Note:
*PCI Local Bus Specification, Version 2.1, Section 4.2.2.2.
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