TTL Output Module Timing5 t" />
參數(shù)資料
型號(hào): A42MX36-PQG240I
廠商: Microsemi SoC
文件頁數(shù): 102/142頁
文件大小: 0K
描述: IC FPGA MX SGL CHIP 54K 240-PQFP
標(biāo)準(zhǔn)包裝: 24
系列: MX
RAM 位總計(jì): 2560
輸入/輸出數(shù): 202
門數(shù): 54000
電源電壓: 3 V ~ 3.6 V,4.5 V ~ 5.5 V
安裝類型: 表面貼裝
工作溫度: -40°C ~ 85°C
封裝/外殼: 240-BFQFP
供應(yīng)商設(shè)備封裝: 240-PQFP(32x32)
40MX and 42MX FPGA Families
1- 58
R e v i sio n 1 1
TTL Output Module Timing5
tDLH
Data-to-Pad HIGH
3.4
3.8
4.3
5.1
7.1
ns
tDHL
Data-to-Pad LOW
4.0
4.5
5.1
6.1
8.3
ns
tENZH
Enable Pad Z to HIGH
3.7
4.1
4.6
5.5
7.6
ns
tENZL
Enable Pad Z to LOW
4.1
4.5
5.1
6.1
8.5
ns
tENHZ
Enable Pad HIGH to Z
6.9
7.6
8.6
10.2
14.2
ns
tENLZ
Enable Pad LOW to Z
7.5
8.3
9.4
11.1
15.5
ns
tGLH
G-to-Pad HIGH
5.8
6.5
7.3
8.6
12.0
ns
tGHL
G-to-Pad LOW
5.8
6.5
7.3
8.6
12.0
ns
tLSU
I/O Latch Set-Up
0.7
0.8
0.9
1.0
1.4
ns
tLH
I/O Latch Hold
0.0
ns
tLCO
I/O Latch Clock-to-Out
(Pad-to-Pad), 64 Clock Loading
8.7
9.7
10.9
12.9
18.0
ns
tACO
Array Clock-to-Out
(Pad-to-Pad),64 Clock Loading
12.2
13.5
15.4
18.1
25.3
ns
dTLH
Capacity Loading, LOW to HIGH
0.00
0.10
0.01 ns/pF
dTHL
Capacity Loading, HIGH to LOW
0.09
0.10
0.10 ns/pF
Table 1-33 A42MX09 Timing Characteristics (Nominal 3.3 V Operation) (continued)
(Worst-Case Commercial Conditions, VCCA = 3.0 V, TJ = 70°C)
–3 Speed
–2 Speed
–1 Speed
Std Speed
–F Speed
Units
Parameter / Description
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max.
Notes:
1. For dual-module macros, use tPD1 + tRD1 + tPDn, tCO + tRD1 + tPDn, or tPD1 + tRD1 + tSUD, whichever is appropriate.
2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for
estimating device performance. Post-route timing analysis or simulation is required to determine actual performance.
3. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules
can be obtained from the Timer utility.
4. Set-up and hold timing parameters for the input buffer latch are defined with respect to the PAD and the D input. External
setup/hold timing parameters must account for delay from an external PAD signal to the G inputs. Delay from an external
PAD signal to the G input subtracts (adds) to the internal setup (hold) time.
5. Delays based on 35 pF loading.
相關(guān)PDF資料
PDF描述
A3PE3000L-1FG896 IC FPGA 1KB FLASH 3M 896-FBGA
IDT71V546S100PFG IC SRAM 4MBIT 100MHZ 100TQFP
A3PE3000L-1FGG896 IC FPGA 1KB FLASH 3M 896-FBGA
ASM11DREI CONN EDGECARD 22POS .156 EYELET
M1A3PE3000L-1FG896 IC FPGA 1KB FLASH 3M 896-FBGA
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
A42MX36-PQG240M 制造商:Microsemi Corporation 功能描述:FPGA 54K GATES 1184 CELLS 79MHZ/131MHZ 0.45UM 3.3V/5V 240PQF - Trays 制造商:Microsemi Corporation 功能描述:IC FPGA 202 I/O 240PQFP
A42N3009 制造商:Pentair Technical Products / Hoffman 功能描述:Enclosure 42.00x30.00x9.25 Gray, 42.00x30.00x9.25, Steel 制造商:Pentair Technical Products / Hoffman 功能描述:ENCLOSURE, JUNCTION BOX, STEEL, GRAY, Enclosure Type:Junction Box, Enclosure Mat 制造商:Pentair Technical Products / Hoffman 功能描述:ENCLOSURE, JUNCTION BOX, STEEL, GRAY, Enclosure Type:Junction Box, Enclosure Material:Steel, Body Color:Grey, External Height - Imperial:42", External Height - Metric:1067mm, External Width - Imperial:30", IP Rating:IP30, NEMA Type:1, RoHS Compliant: Yes
A42N3013 制造商:Pentair Technical Products / Hoffman 功能描述:Enclosure 42.00x30.00x13.25 Gray, 42.00x30.00x13.25, Steel
A-42N3013 制造商:Pentair Technical Products / Hoffman 功能描述:Enclosure 42.00x30.00x13.25
A42N3609 制造商:Pentair Technical Products / Hoffman 功能描述:Enclosure 42.00x36.00x9.25 Gray, 42.00x36.00x9.25, Steel