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參數(shù)資料
型號： A42MX36-PQG240I
廠商： Microsemi SoC
文件頁數(shù)： 89/142頁
文件大?。?/td> 0K
描述： IC FPGA MX SGL CHIP 54K 240-PQFP
標準包裝： 24
系列： MX
RAM 位總計： 2560
輸入/輸出數(shù)： 202
門數(shù)： 54000
電源電壓： 3 V ~ 3.6 V，4.5 V ~ 5.5 V
安裝類型： 表面貼裝
工作溫度： -40°C ~ 85°C
封裝/外殼： 240-BFQFP
供應商設備封裝： 240-PQFP（32x32）
40MX and 42MX FPGA Families
1- 46
R e v i sio n 1 1
Table 1-30 A40MX04 Timing Characteristics (Nominal 5.0 V Operation)
(Worst-Case Commercial Conditions, VCC = 4.75 V, TJ = 70°C)
–3 Speed
–2 Speed
–1 Speed
Std Speed
–F Speed
Units
Parameter / Description
Min. Max.
Min.
Max. Min. Max. Min. Max. Min. Max.
Logic Module Propagation Delays
tPD1
Single Module
1.2
1.4
1.6
1.9
2.7
ns
tPD2
Dual-Module Macros
2.3
3.1
3.5
4.1
5.7
ns
tCO
Sequential Clock-to-Q
1.2
1.4
1.6
1.9
2.7
ns
tGO
Latch G-to-Q
1.2
1.4
1.6
1.9
2.7
ns
tRS
Flip-Flop (Latch) Reset-to-Q
1.2
1.4
1.6
1.9
2.7
ns
Logic Module Predicted Routing Delays1
tRD1
FO = 1 Routing Delay
1.2
1.6
1.8
2.1
3.0
ns
tRD2
FO = 2 Routing Delay
1.9
2.2
2.5
2.9
4.1
ns
tRD3
FO = 3 Routing Delay
2.4
2.8
3.2
3.7
5.2
ns
tRD4
FO = 4 Routing Delay
2.9
3.4
3.9
4.5
6.3
ns
tRD8
FO = 8 Routing Delay
5.0
5.8
6.6
7.8
10.9
ns
Logic Module Sequential Timing2
tSUD
Flip-Flop (Latch)
Data Input Set-Up
3.1
3.5
4.0
4.7
6.6
ns
tHD
3
Flip-Flop (Latch)
Data Input Hold
0.0
ns
tSUENA
Flip-Flop (Latch)
Enable Set-Up
3.1
3.5
4.0
4.7
6.6
ns
tHENA
Flip-Flop (Latch)
Enable Hold
0.0
ns
tWCLKA
Flip-Flop (Latch)
Clock Active Pulse Width
3.3
3.8
4.3
5.0
7.0
ns
tWASYN Flip-Flop (Latch)
Asynchronous Pulse Width
3.3
3.8
4.3
5.0
7.0
ns
tA
Flip-Flop Clock Input Period
4.8
5.6
6.3
7.5
10.4
ns
fMAX
Flip-Flop (Latch)
Clock Frequency
(FO = 128)
181
167
154
134
80
MHz
Input Module Propagation Delays
tINYH
Pad-to-Y HIGH
0.7
0.8
0.9
1.1
1.5
ns
tINYL
Pad-to-Y LOW
0.6
0.7
0.8
1.0
1.3
ns
Notes:
1. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for
estimating device performance. Post-route timing analysis or simulation is required to determine actual performance.
2. Set-up times assume fanout of 3. Further testing information can be obtained from the Timer utility.
3. The hold time for the DFME1A macro may be greater than 0 ns. Use the Timer utility from the Designer software to
check the hold time for this macro.
4. Delays based on 35 pF loading.
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相關代理商/技術參數(shù)
參數(shù)描述
A42MX36-PQG240M 制造商:Microsemi Corporation 功能描述:FPGA 54K GATES 1184 CELLS 79MHZ/131MHZ 0.45UM 3.3V/5V 240PQF - Trays 制造商:Microsemi Corporation 功能描述:IC FPGA 202 I/O 240PQFP
A42N3009 制造商:Pentair Technical Products / Hoffman 功能描述:Enclosure 42.00x30.00x9.25 Gray, 42.00x30.00x9.25, Steel 制造商:Pentair Technical Products / Hoffman 功能描述:ENCLOSURE, JUNCTION BOX, STEEL, GRAY, Enclosure Type:Junction Box, Enclosure Mat 制造商:Pentair Technical Products / Hoffman 功能描述:ENCLOSURE, JUNCTION BOX, STEEL, GRAY, Enclosure Type:Junction Box, Enclosure Material:Steel, Body Color:Grey, External Height - Imperial:42", External Height - Metric:1067mm, External Width - Imperial:30", IP Rating:IP30, NEMA Type:1, RoHS Compliant: Yes
A42N3013 制造商:Pentair Technical Products / Hoffman 功能描述:Enclosure 42.00x30.00x13.25 Gray, 42.00x30.00x13.25, Steel
A-42N3013 制造商:Pentair Technical Products / Hoffman 功能描述:Enclosure 42.00x30.00x13.25
A42N3609 制造商:Pentair Technical Products / Hoffman 功能描述:Enclosure 42.00x36.00x9.25 Gray, 42.00x36.00x9.25, Steel
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