參數(shù)資料
型號(hào)： A54SX08-1PL84M
英文描述： Field Programmable Gate Array (FPGA)
中文描述： 現(xiàn)場(chǎng)可編程門陣列（FPGA）
文件頁(yè)數(shù)： 9/36頁(yè)
文件大?。?/td> 833K
代理商： A54SX08-1PL84M
v2.0
9
54SX Family FPGAs RadTolerant and HiRel
Boundary Scan Testing (BST)
All RT54SX devices are IEEE 1149.1 (JTAG) compliant.
They offer superior diagnostic and testing capabilities by
providing Boundary Scan Testing (BST) and probing
capabilities. These functions are controlled through the
special test pins in conjunction with the program fuse. The
functionality of each pin is described in
Table 2
.
Figure 10
is a block diagram of the RT54SX JTAG circuitry.
Configuring Diagnostic Pins
The JTAG and Probe pins (TDI, TCK, TMS, TDO, PRA, and
PRB) are placed in the desired mode by selecting the
appropriate check boxes in the
“
Variation
”
dialog window.
This dialog window is accessible through the Design Setup
Wizard under the Tools menu in Actel
’
s Designer software.
TRST pin
The TRST pin functions as a Boundary Scan Reset pin. The
TRST pin is an asynchronous, active-low input to initialize
or reset the BST circuit. An internal pull-up resistor is
automatically enabled on the TRST pin.
Dedicated Test Mode
When the
“
Reserve JTAG
”
box is checked in the Designer
software, the RT54SX is placed in Dedicated Test mode, which
configures the TDI, TCK, and TDO pins for BST or in-circuit
verification with Silicon Explorer II. An internal pull-up resistor
is automatically enabled on both the TMS and TDI pins. In
dedicated test mode, TCK, TDI, and TDO are dedicated test pins
and become unavailable for pin assignment in the Pin Editor.
The TMS pin will function as specified in the IEEE 1149.1
(JTAG) Specification.
Flexible Mode
When the
“
Reserve JTAG
”
box is not selected (default setting
in Designer software), the RT54SX is placed in flexible mode,
which allows the TDI, TCK, and TDO pins to function as user
I/Os or BST pins. In this mode the internal pull-up resistors on
the TMS and TDI pins are disabled. An external 10k
pull-up
resistor to VCCI is required on the TMS pin.
The TDI, TCK, and TDO pins are transformed from user I/Os
into BST pins when a rising edge on TCK is detected while
TMS is at logical low. Once the BST pins are in test mode
they will remain in BST mode until the internal BST state
Table 2
Boundary Scan Pin Functionality
Program Fuse Blown
(Dedicated Test Mode)
Program Fuse Not Blown
(Flexible Mode)
TCK, TDI, TDO are
dedicated test pins
No need for pull-up resistor
for TMS
TCK, TDI, TDO are flexible
and may be used as I/Os
Use a pull-up resistor of
10k
on TMS
Figure 10
RT54SX JTAG Circuitry
Instruction Register (IR)
Data Registers (DRs)
clocks and/or controls
TAP Controller
output
stage
0
1
TDO
TDI
TMS
TCK
TRST external
hard-wired pin
相關(guān)PDF資料
PDF描述
A54SX08-1TQ144 Field Programmable Gate Array (FPGA)
A54SX08-1TQ144I Field Programmable Gate Array (FPGA)
A54SX08-1TQ144M Field Programmable Gate Array (FPGA)
A54SX08-1TQ176 Field Programmable Gate Array (FPGA)
A54SX08-1TQ176I Field Programmable Gate Array (FPGA)
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
A54SX08-1PLG84 功能描述:IC FPGA SX 12K GATES 84-PLCC RoHS:是 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場(chǎng)可編程門陣列） 系列:SX 標(biāo)準(zhǔn)包裝:40 系列:SX-A LAB/CLB數(shù):6036 邏輯元件/單元數(shù):- RAM 位總計(jì):- 輸入/輸出數(shù):360 門數(shù):108000 電源電壓:2.25 V ~ 5.25 V 安裝類型:表面貼裝 工作溫度:0°C ~ 70°C 封裝/外殼:484-BGA 供應(yīng)商設(shè)備封裝:484-FPBGA（27X27）
A54SX08-1PLG84I 功能描述:IC FPGA SX 12K GATES 84-PLCC RoHS:是 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場(chǎng)可編程門陣列） 系列:SX 標(biāo)準(zhǔn)包裝:40 系列:SX-A LAB/CLB數(shù):6036 邏輯元件/單元數(shù):- RAM 位總計(jì):- 輸入/輸出數(shù):360 門數(shù):108000 電源電壓:2.25 V ~ 5.25 V 安裝類型:表面貼裝 工作溫度:0°C ~ 70°C 封裝/外殼:484-BGA 供應(yīng)商設(shè)備封裝:484-FPBGA（27X27）
A54SX08-1PQ208 功能描述:IC FPGA SX 12K GATES 208-PQFP RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場(chǎng)可編程門陣列） 系列:SX 標(biāo)準(zhǔn)包裝:40 系列:SX-A LAB/CLB數(shù):6036 邏輯元件/單元數(shù):- RAM 位總計(jì):- 輸入/輸出數(shù):360 門數(shù):108000 電源電壓:2.25 V ~ 5.25 V 安裝類型:表面貼裝 工作溫度:0°C ~ 70°C 封裝/外殼:484-BGA 供應(yīng)商設(shè)備封裝:484-FPBGA（27X27）
A54SX08-1PQ208I 功能描述:IC FPGA SX 12K GATES 208-PQFP RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場(chǎng)可編程門陣列） 系列:SX 標(biāo)準(zhǔn)包裝:40 系列:SX-A LAB/CLB數(shù):6036 邏輯元件/單元數(shù):- RAM 位總計(jì):- 輸入/輸出數(shù):360 門數(shù):108000 電源電壓:2.25 V ~ 5.25 V 安裝類型:表面貼裝 工作溫度:0°C ~ 70°C 封裝/外殼:484-BGA 供應(yīng)商設(shè)備封裝:484-FPBGA（27X27）
A54SX08-1PQ208M 制造商:未知廠家 制造商全稱:未知廠家 功能描述:54SX Family FPGAs
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*