參數(shù)資料
型號(hào)： A54SX08-3VQ100
英文描述： Field Programmable Gate Array (FPGA)
中文描述： 現(xiàn)場(chǎng)可編程門陣列（FPGA）
文件頁(yè)數(shù)： 6/36頁(yè)
文件大?。?/td> 833K
代理商： A54SX08-3VQ100
54SX Family FPGAs RadTolerant and HiRel
6
v2.0
Routing Resources
Clusters and SuperClusters can be connected through the
use of two innovative local routing resources called
FastConnect
and
DirectConnect
that enable extremely fast
and predictable interconnections of modules within
Clusters and SuperClusters (see
Figure 6
and
Figure 7 on
page 7
). This routing architecture also dramatically reduces
the number of antifuses required to complete a circuit,
ensuring the highest possible performance.
DirectConnect is a horizontal routing resource that provides
connections from a C-cell to its neighboring R-cell in a given
SuperCluster. DirectConnect uses a hard-wired signal path
requiring no programmable interconnection to achieve its
fast signal propagation time of less than 0.1 ns.
FastConnect enables horizontal routing between any two
logic modules within a given SuperCluster, and vertical
routing with the SuperCluster immediately below it. Only
one programmable connection is used in a FastConnect
path, delivering maximum pin-to-pin propagation of 0.4 ns.
Figure 4
C-Cell
Figure 5
Cluster Organization
D0
D1
D2
D3
DB
A0
B0
A1
B1
Sa
Sb
Y
Type 1 SuperCluster
Type 2 SuperCluster
Cluster 1
Cluster 2
Cluster 2
Cluster 1
R-Cell
C-Cell
D0
D1
D2
D3
DB
A0
B0
A1
B1
Sa
Sb
Y
Direct
Connect
Input
CLKA,
CLKB
HCLK
CKS
CKP
CLRB
PSET
Y
D
Q
Routed
Data Input
S0
S1
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