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參數(shù)資料
| 型號(hào)： | A54SX08P-3TQ208M |
| 廠商： | Electronic Theatre Controls, Inc. |
| 元件分類： | FPGA |
| 英文描述： | 54SX Family FPGAs |
| 中文描述： | 54SX家庭的FPGA |
| 文件頁數(shù)： | 4/57頁 |
| 文件大?。?/td> | 415K |
| 代理商： | A54SX08P-3TQ208M |
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5 4 S X F a m ily F P G A s
4
v3.1
S X F a m ily A rc hit e c t ure
The SX family architecture was designed to satisfy
next-generation performance and integration requirements
for production-volume designs in a broad range of
applications.
P rog ra m m a ble Int e rc onne c t E le m e nt
The SX family provides efficient use of silicon by locating the
routing interconnect resources between the Metal 2 (M2)
and Metal 3 (M3) layers (
Figure1
). This completely
eliminates the channels of routing and interconnect
resources between logic modules (as implemented on SRAM
FPGAs and previous generations of antifuse FPGAs), and
enables the entire floor of the device to be spanned with an
uninterrupted grid of logic modules.
Interconnection between these logic modules is achieved
using Actel’s patented metal-to-metal programmable
antifuse interconnect elements, which are embedded
between the M2 and M3 layers. The antifuses are normally
open circuit and, when programmed, form a permanent
low-impedance connection.
The extremely small size of these interconnect elements
gives the SX family abundant routing resources and provides
excellent protection against design pirating. Reverse
engineering is virtually impossible because it is extremely
difficult to distinguish between programmed and
unprogrammed antifuses, and there is no configuration
bitstream to intercept.
Additionally, the interconnect (i.e., the antifuses and metal
tracks) have lower capacitance and lower resistance than
any other device of similar capacity, leading to the fastest
signal propagation in the industry.
L og ic Module D e s ig n
The SX family architecture is described as a
“sea-of-modules” architecture because the entire floor of
the device is covered with a grid of logic modules with
virtually no chip area lost to interconnect elements or
routing. Actel’s SX family provides two types of logic
modules, the register cell (R-cell) and the combinatorial
cell (C-cell).
The R-cell contains a flip-flop featuring asynchronous clear,
asynchronous preset, and clock enable (using the S0 and S1
lines) control signals (
Figure2 on page5
). The R-cell
registers feature programmable clock polarity selectable on
a register-by-register basis. This provides additional
flexibility while allowing mapping of synthesized functions
into the SX FPGA. The clock source for the R-cell can be
chosen from either the hard-wired clock or the routed clock.
Figure 1
SX Family Interconnect Elements
Silicon Substrate
Tungsten Plug
Contact
Metal 1
Metal 2
Metal 3
Routing Tracks
Amorphous Silicon/
Dielectric Antifuse
Tungsten Plug Via
Tungsten Plug Via
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| A54SX08P-3TQ208PP | 54SX Family FPGAs |
| A54SX08P-3VQ208 | 54SX Family FPGAs |
| A54SX16 | Quad 2-input positive-NAND gates 14-SO 0 to 70 |
| A54SX32 | Quad 2-input positive-NAND gates 8-SO 0 to 70 |
| A54SX32-1BG208I | Quad 2-input positive-NAND gates 8-SO 0 to 70 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| A54SX08P-3TQ208PP | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:54SX Family FPGAs |
| A54SX08P-3TQG208 | 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:SX Family FPGAs |
| A54SX08-P-3TQG208I | 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:SX Family FPGAs |
| A54SX08P-3TQG208I | 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:SX Family FPGAs |
| A54SX08-P-3TQG208M | 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:SX Family FPGAs |
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